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An epoll-driven, neutral transfer-event bus that connects sensors and input actuators to one or more controls, bidirectionally. It owns the transfer context and events — delivery order, priority, protocol-level timing, and an interrupt-driven event model over fd sources (eventfd/timerfd/sockets) — and stays agnostic to both the sensor/input drivers and the control. What lives here: - memctx: a coherent address-space context per endpoint — the guest address-space root paired with a pre-opened read-only RAM-region fd, with per-endpoint epoch invalidation and retained replay to late subscribers. Perception lives in out-of-tree sensor libraries that consume this datum read-only. - exclusive-ownership leases for destructive resource classes (input, power, memory-write). - write-signaled memory writes (MEMWRITE): an atomic write to guest memory routed through the seam under an exclusive lease, never a writable mapping. - a host-management seam for VM lifecycle/status and a neutral input-injection command path. - multi-VM endpoints; capability-gated, audited control authorization over an in-process or unix-socket transport. Builds against headers only by default (a stub mode that exercises the seam without a VM); armed builds link the real sensor/input libraries behind flags. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
22 lines
1.1 KiB
C
22 lines
1.1 KiB
C
#ifndef VMSIG_H
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#define VMSIG_H
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/* vmsig.h — umbrella header for the signaling layer of the SISC paradigm.
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*
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* vmsig binds the three SI repos (sensors vmie/vgpustream + input vmctl) to the control
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* (algorithm OR human), bidirectionally translating transfer events. The layer itself
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* contains NO sensing, actuation, or decision/behavioral-timing logic.
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*
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* Application wiring: create the context (vmsig_ctx_new) -> core (vmsig_core_new) ->
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* register per-VM adapters (vmsig_core_add_adapter) and control
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* (vmsig_core_add_control) -> vmsig_core_run. */
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#include "vmsig_event.h" /* neutral transfer-event model + payload */
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#include "vmsig_memctx.h" /* address-space context handoff contract (kcr3+locator) */
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#include "vmsig_ctx.h" /* transfer context: priority/seq/protocol timing */
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#include "vmsig_adapter.h" /* unified SI adapter interface + factories */
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#include "vmsig_control.h" /* control-agnostic seam + reference in-proc */
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#include "vmsig_core.h" /* epoll core */
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#endif /* VMSIG_H */
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