vatrog-vm-signaling/include/vmsig.h

#ifndef VMSIG_H
#define VMSIG_H

/* vmsig.h — umbrella header for the signaling layer of the SISC paradigm.
 *
 * vmsig binds the three SI repos (sensors vmie/vgpustream + input vmctl) to the control
 * (algorithm OR human), bidirectionally translating transfer events. The layer itself
 * contains NO sensing, actuation, or decision/behavioral-timing logic.
 *
 * Application wiring: create the context (vmsig_ctx_new) -> core (vmsig_core_new) ->
 * register per-VM adapters (vmsig_core_add_adapter) and control
 * (vmsig_core_add_control) -> vmsig_core_run. */

#include "vmsig_event.h"     /* neutral transfer-event model + payload         */
#include "vmsig_memctx.h"    /* address-space context handoff contract (kcr3+locator) */
#include "vmsig_ctx.h"       /* transfer context: priority/seq/protocol timing */
#include "vmsig_adapter.h"   /* unified SI adapter interface + factories        */
#include "vmsig_control.h"   /* control-agnostic seam + reference in-proc       */
#include "vmsig_core.h"      /* epoll core                                      */

#endif /* VMSIG_H */