simd: detect and surface support for Intel SHA512 extensions

Recent Intel CPUs (starting with Arrow Lake and Lunar Lake) include new
vectorised SHA512 instructions. Detect them and make them available to
the rest of the system.

Note the internal name "sha512ext". This is to disambiguate from other
uses of "sha512".

Sponsored-by: TrueNAS
Reviewed-by: Tony Hutter <hutter2@llnl.gov>
Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed-by: Attila Fülöp <attila@fueloep.org>
Signed-off-by: Rob Norris <rob.norris@truenas.com>
Closes #18233

lib/libspl/include/sys/simd.h

@@ -23,6 +23,7 @@
 /*
  * Copyright (c) 2006 Sun Microsystems, Inc.  All rights reserved.
  * Copyright (c) 2022 Tino Reichardt <milky-zfs@mcmilk.de>
+ * Copyright (c) 2026, TrueNAS.
  */
 
 #ifndef _LIBSPL_SYS_SIMD_H
@@ -104,7 +105,8 @@ typedef enum cpuid_inst_sets {
 	MOVBE,
 	SHA_NI,
 	VAES,
-	VPCLMULQDQ
+	VPCLMULQDQ,
+	SHA512EXT,
 } cpuid_inst_sets_t;
 
 /*
@@ -132,6 +134,7 @@ typedef struct cpuid_feature_desc {
 #define	_VAES_BIT		(1U << 9)
 #define	_VPCLMULQDQ_BIT		(1U << 10)
 #define	_SHA_NI_BIT		(1U << 29)
+#define	_SHA512_BIT		(1U << 0)
 
 /*
  * Descriptions of supported instruction sets
@@ -163,6 +166,7 @@ static const cpuid_feature_desc_t cpuid_features[] = {
 	[SHA_NI]	= {7U, 0U, _SHA_NI_BIT,		EBX	},
 	[VAES]		= {7U, 0U, _VAES_BIT,		ECX	},
 	[VPCLMULQDQ]	= {7U, 0U, _VPCLMULQDQ_BIT,	ECX	},
+	[SHA512EXT]	= {7U, 1U, _SHA512_BIT,		EAX	},
 };
 
 /*
@@ -239,6 +243,7 @@ CPUID_FEATURE_CHECK(movbe, MOVBE);
 CPUID_FEATURE_CHECK(shani, SHA_NI);
 CPUID_FEATURE_CHECK(vaes, VAES);
 CPUID_FEATURE_CHECK(vpclmulqdq, VPCLMULQDQ);
+CPUID_FEATURE_CHECK(sha512ext, SHA512EXT);
 
 /*
  * Detect register set support
@@ -407,6 +412,15 @@ zfs_vpclmulqdq_available(void)
 	return (__cpuid_has_vpclmulqdq());
 }
 
+/*
+ * Check if SHA512 instructions are available
+ */
+static inline boolean_t
+zfs_sha512ext_available(void)
+{
+	return (__cpuid_has_sha512ext());
+}
+
 /*
  * AVX-512 family of instruction sets:
  *