feat(cpuid): leaf 0x15 TSC / core-crystal ratio (patch 0026)
Real Intel CPUs enumerate leaf 0x15 (TSC/crystal ratio); QEMU returns 0. Fill it consistently with leaf 0x16 (TSC == base freq). Intel persona only. Module getters spoof_cpu_crystal_hz/tsc_num/tsc_den. Inert without a seed. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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@@ -29,6 +29,12 @@ int spoof_cpu_bus_mhz(int def)
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{
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return spoof_on() ? 100 : def;
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}
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/* CPUID leaf 0x15 (TSC / nominal core-crystal ratio). Intel enumerates it; AMD does
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* not, so return the default for an AMD persona. Chosen so TSC == base frequency:
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* ECX(24 MHz) * EBX(base_mhz) / EAX(24) = base_mhz * 1e6 Hz, consistent with 0x16. */
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int spoof_cpu_crystal_hz(int def) { return (spoof_on() && !spoof_anchor_vendor()) ? 24000000 : def; }
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int spoof_cpu_tsc_num(int def) { return (spoof_on() && !spoof_anchor_vendor()) ? spoof_cpu_base_mhz(0) : def; }
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int spoof_cpu_tsc_den(int def) { return (spoof_on() && !spoof_anchor_vendor()) ? 24 : def; }
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/* Microcode revision, returned already positioned for the MSR (IA32_UCODE_REV
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* 0x8B): Intel reports the revision in bits 63:32, AMD the patch level in 31:0.
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* Stock QEMU/KVM defaults (Intel 0x1_00000000, AMD 0x01000065) follow the same
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@@ -52,6 +52,9 @@ const char *spoof_kvm_signature(const char *def); /* 12 bytes; vendor-ancho
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int spoof_cpu_base_mhz(int def); /* CPUID leaf 0x16 base freq */
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int spoof_cpu_max_mhz(int def); /* CPUID leaf 0x16 max freq */
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int spoof_cpu_bus_mhz(int def); /* CPUID leaf 0x16 bus freq */
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int spoof_cpu_crystal_hz(int def); /* CPUID leaf 0x15 ECX (Intel core crystal) */
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int spoof_cpu_tsc_num(int def); /* leaf 0x15 EBX (TSC ratio numerator) */
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int spoof_cpu_tsc_den(int def); /* leaf 0x15 EAX (TSC ratio denominator) */
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uint64_t spoof_cpu_microcode(uint64_t def); /* IA32_UCODE_REV, vendor-positioned */
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/* ---- PCI (spoof-pci.c) ---------------------------------------------------- */
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