9be61fa466
fixes for: * CVE-2018-12126 * CVE-2018-12127 * CVE-2018-12130 * CVE-2019-11091 adds the md-clear cpuflag. Not included by default in any Intel CPU model. Must be explicitly turned on for all Intel CPU models. Requires the host CPU microcode to support this feature before it can be used for guest CPUs. Signed-off-by: Oguz Bektas <o.bektas@proxmox.com>
114 lines
3.9 KiB
Diff
114 lines
3.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Robert Hoo <robert.hu@linux.intel.com>
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Date: Mon, 15 Oct 2018 12:47:25 +0800
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Subject: [PATCH 7/9] x86: define a new MSR based feature word --
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FEATURE_WORDS_ARCH_CAPABILITIES
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Note RSBA is specially treated -- no matter host support it or not, qemu
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pretends it is supported.
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
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[ehabkost: removed automatic enabling of RSBA]
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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---
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target/i386/cpu.c | 24 +++++++++++++++++++++++-
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target/i386/cpu.h | 8 ++++++++
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target/i386/kvm.c | 11 +++++++++++
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3 files changed, 42 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index d2985144a3..a64aa8793e 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1141,6 +1141,27 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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},
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.tcg_features = ~0U,
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},
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+ /*Below are MSR exposed features*/
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+ [FEAT_ARCH_CAPABILITIES] = {
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+ .type = MSR_FEATURE_WORD,
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+ .feat_names = {
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+ "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
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+ "ssb-no", NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ },
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+ .msr = {
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+ .index = MSR_IA32_ARCH_CAPABILITIES,
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+ .cpuid_dep = {
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+ FEAT_7_0_EDX,
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+ CPUID_7_0_EDX_ARCH_CAPABILITIES
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+ }
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+ },
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+ },
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};
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typedef struct X86RegisterInfo32 {
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@@ -3581,7 +3602,8 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
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wi->cpuid.reg);
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break;
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case MSR_FEATURE_WORD:
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- r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
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+ r = kvm_arch_get_supported_msr_feature(kvm_state,
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+ wi->msr.index);
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break;
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}
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} else if (hvf_enabled()) {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index fb2f5f6ebc..ae54a98249 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -502,6 +502,7 @@ typedef enum FeatureWord {
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FEAT_6_EAX, /* CPUID[6].EAX */
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FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
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FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
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+ FEAT_ARCH_CAPABILITIES,
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FEATURE_WORDS,
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} FeatureWord;
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@@ -727,6 +728,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
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#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
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+/* MSR Feature Bits */
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+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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+#define MSR_ARCH_CAP_RSBA (1U << 2)
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+#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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+
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#ifndef HYPERV_SPINLOCK_NEVER_RETRY
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#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
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#endif
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index cd45c79169..0b7fcb4f7f 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -1936,6 +1936,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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}
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#endif
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+ /* If host supports feature MSR, write down. */
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+ if (kvm_feature_msrs) {
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+ int i;
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+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
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+ if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
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+ env->features[FEAT_ARCH_CAPABILITIES]);
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+ break;
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+ }
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+ }
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+
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/*
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* The following MSRs have side effects on the guest or are too heavy
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* for normal writeback. Limit them to reset or full state updates.
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--
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2.20.1
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