9be61fa466
fixes for: * CVE-2018-12126 * CVE-2018-12127 * CVE-2018-12130 * CVE-2019-11091 adds the md-clear cpuflag. Not included by default in any Intel CPU model. Must be explicitly turned on for all Intel CPU models. Requires the host CPU microcode to support this feature before it can be used for guest CPUs. Signed-off-by: Oguz Bektas <o.bektas@proxmox.com>
486 lines
18 KiB
Diff
486 lines
18 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Robert Hoo <robert.hu@linux.intel.com>
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Date: Mon, 15 Oct 2018 12:47:24 +0800
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Subject: [PATCH 6/9] x86: Data structure changes to support MSR based features
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Add FeatureWordType indicator in struct FeatureWordInfo.
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Change feature_word_info[] accordingly.
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Change existing functions that refer to feature_word_info[] accordingly.
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1539578845-37944-3-git-send-email-robert.hu@linux.intel.com>
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[ehabkost: fixed hvf_enabled() case]
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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---
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target/i386/cpu.c | 197 +++++++++++++++++++++++++++++++++-------------
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1 file changed, 142 insertions(+), 55 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 1d74be02ce..d2985144a3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -770,17 +770,36 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
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/* missing:
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CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
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+typedef enum FeatureWordType {
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+ CPUID_FEATURE_WORD,
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+ MSR_FEATURE_WORD,
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+} FeatureWordType;
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+
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typedef struct FeatureWordInfo {
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+ FeatureWordType type;
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/* feature flags names are taken from "Intel Processor Identification and
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* the CPUID Instruction" and AMD's "CPUID Specification".
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* In cases of disagreement between feature naming conventions,
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* aliases may be added.
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*/
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const char *feat_names[32];
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- uint32_t cpuid_eax; /* Input EAX for CPUID */
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- bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
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- uint32_t cpuid_ecx; /* Input ECX value for CPUID */
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- int cpuid_reg; /* output register (R_* constant) */
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+ union {
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+ /* If type==CPUID_FEATURE_WORD */
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+ struct {
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+ uint32_t eax; /* Input EAX for CPUID */
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+ bool needs_ecx; /* CPUID instruction uses ECX as input */
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+ uint32_t ecx; /* Input ECX value for CPUID */
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+ int reg; /* output register (R_* constant) */
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+ } cpuid;
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+ /* If type==MSR_FEATURE_WORD */
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+ struct {
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+ uint32_t index;
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+ struct { /*CPUID that enumerate this MSR*/
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+ FeatureWord cpuid_class;
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+ uint32_t cpuid_flag;
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+ } cpuid_dep;
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+ } msr;
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+ };
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uint32_t tcg_features; /* Feature flags supported by TCG */
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uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
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uint32_t migratable_flags; /* Feature flags known to be migratable */
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@@ -790,6 +809,7 @@ typedef struct FeatureWordInfo {
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static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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[FEAT_1_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"fpu", "vme", "de", "pse",
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"tsc", "msr", "pae", "mce",
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@@ -800,10 +820,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"fxsr", "sse", "sse2", "ss",
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"ht" /* Intel htt */, "tm", "ia64", "pbe",
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},
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- .cpuid_eax = 1, .cpuid_reg = R_EDX,
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+ .cpuid = {.eax = 1, .reg = R_EDX, },
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.tcg_features = TCG_FEATURES,
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},
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[FEAT_1_ECX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
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"ds-cpl", "vmx", "smx", "est",
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@@ -814,7 +835,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"tsc-deadline", "aes", "xsave", NULL /* osxsave */,
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"avx", "f16c", "rdrand", "hypervisor",
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},
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- .cpuid_eax = 1, .cpuid_reg = R_ECX,
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+ .cpuid = { .eax = 1, .reg = R_ECX, },
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.tcg_features = TCG_EXT_FEATURES,
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},
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/* Feature names that are already defined on feature_name[] but
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@@ -823,6 +844,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
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*/
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[FEAT_8000_0001_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
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NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
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@@ -833,10 +855,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
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NULL, "lm", "3dnowext", "3dnow",
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},
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- .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
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.tcg_features = TCG_EXT2_FEATURES,
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},
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[FEAT_8000_0001_ECX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"lahf-lm", "cmp-legacy", "svm", "extapic",
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"cr8legacy", "abm", "sse4a", "misalignsse",
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@@ -847,7 +870,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"perfctr-nb", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
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+ .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
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.tcg_features = TCG_EXT3_FEATURES,
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/*
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* TOPOEXT is always allowed but can't be enabled blindly by
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@@ -857,6 +880,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.no_autoenable_flags = CPUID_EXT3_TOPOEXT,
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},
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[FEAT_C000_0001_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, "xstore", "xstore-en",
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NULL, NULL, "xcrypt", "xcrypt-en",
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@@ -867,10 +891,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
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.tcg_features = TCG_EXT4_FEATURES,
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},
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[FEAT_KVM] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
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"kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
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@@ -881,10 +906,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"kvmclock-stable-bit", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
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+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
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.tcg_features = TCG_KVM_FEATURES,
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},
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[FEAT_KVM_HINTS] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"kvm-hint-dedicated", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@@ -895,7 +921,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
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.tcg_features = TCG_KVM_FEATURES,
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/*
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* KVM hints aren't auto-enabled by -cpu host, they need to be
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@@ -904,6 +930,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.no_autoenable_flags = ~0U,
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},
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[FEAT_HYPERV_EAX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
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NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
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@@ -918,9 +945,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
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+ .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
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},
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[FEAT_HYPERV_EBX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
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NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
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@@ -934,9 +962,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
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+ .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
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},
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[FEAT_HYPERV_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
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NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
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@@ -949,9 +978,10 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
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},
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[FEAT_SVM] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"npt", "lbrv", "svm-lock", "nrip-save",
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"tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
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@@ -962,10 +992,11 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
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.tcg_features = TCG_SVM_FEATURES,
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},
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[FEAT_7_0_EBX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"fsgsbase", "tsc-adjust", NULL, "bmi1",
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"hle", "avx2", NULL, "smep",
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@@ -976,12 +1007,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"clwb", "intel-pt", "avx512pf", "avx512er",
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"avx512cd", "sha-ni", "avx512bw", "avx512vl",
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},
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- .cpuid_eax = 7,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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- .cpuid_reg = R_EBX,
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+ .cpuid = {
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+ .eax = 7,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_EBX,
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+ },
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.tcg_features = TCG_7_0_EBX_FEATURES,
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},
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[FEAT_7_0_ECX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, "avx512vbmi", "umip", "pku",
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NULL /* ospke */, NULL, "avx512vbmi2", NULL,
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@@ -992,12 +1026,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, "cldemote", NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 7,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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- .cpuid_reg = R_ECX,
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+ .cpuid = {
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+ .eax = 7,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_ECX,
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+ },
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.tcg_features = TCG_7_0_ECX_FEATURES,
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},
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[FEAT_7_0_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
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NULL, NULL, NULL, NULL,
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@@ -1008,13 +1045,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, "spec-ctrl", NULL,
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NULL, "arch-capabilities", NULL, "ssbd",
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},
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- .cpuid_eax = 7,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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- .cpuid_reg = R_EDX,
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+ .cpuid = {
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+ .eax = 7,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_EDX,
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+ },
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.tcg_features = TCG_7_0_EDX_FEATURES,
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.unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,
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},
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[FEAT_8000_0007_EDX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@@ -1025,12 +1065,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x80000007,
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- .cpuid_reg = R_EDX,
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+ .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
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.tcg_features = TCG_APM_FEATURES,
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.unmigratable_flags = CPUID_APM_INVTSC,
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},
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[FEAT_8000_0008_EBX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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@@ -1041,12 +1081,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0x80000008,
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- .cpuid_reg = R_EBX,
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+ .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
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.tcg_features = 0,
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.unmigratable_flags = 0,
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},
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[FEAT_XSAVE] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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"xsaveopt", "xsavec", "xgetbv1", "xsaves",
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NULL, NULL, NULL, NULL,
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@@ -1057,12 +1097,15 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 0xd,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 1,
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- .cpuid_reg = R_EAX,
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+ .cpuid = {
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+ .eax = 0xd,
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+ .needs_ecx = true, .ecx = 1,
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+ .reg = R_EAX,
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+ },
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.tcg_features = TCG_XSAVE_FEATURES,
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},
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[FEAT_6_EAX] = {
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+ .type = CPUID_FEATURE_WORD,
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.feat_names = {
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NULL, NULL, "arat", NULL,
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NULL, NULL, NULL, NULL,
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@@ -1073,13 +1116,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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},
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- .cpuid_eax = 6, .cpuid_reg = R_EAX,
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+ .cpuid = { .eax = 6, .reg = R_EAX, },
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.tcg_features = TCG_6_EAX_FEATURES,
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},
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[FEAT_XSAVE_COMP_LO] = {
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- .cpuid_eax = 0xD,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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- .cpuid_reg = R_EAX,
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+ .type = CPUID_FEATURE_WORD,
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+ .cpuid = {
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+ .eax = 0xD,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_EAX,
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+ },
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.tcg_features = ~0U,
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.migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
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XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
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@@ -1087,9 +1133,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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XSTATE_PKRU_MASK,
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},
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[FEAT_XSAVE_COMP_HI] = {
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- .cpuid_eax = 0xD,
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- .cpuid_needs_ecx = true, .cpuid_ecx = 0,
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- .cpuid_reg = R_EDX,
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+ .type = CPUID_FEATURE_WORD,
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+ .cpuid = {
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+ .eax = 0xD,
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+ .needs_ecx = true, .ecx = 0,
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+ .reg = R_EDX,
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+ },
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.tcg_features = ~0U,
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},
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};
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@@ -2860,21 +2909,41 @@ static const TypeInfo host_x86_cpu_type_info = {
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#endif
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+static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
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+{
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+ assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
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+
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+ switch (f->type) {
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+ case CPUID_FEATURE_WORD:
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+ {
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+ const char *reg = get_register_name_32(f->cpuid.reg);
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+ assert(reg);
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+ return g_strdup_printf("CPUID.%02XH:%s",
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+ f->cpuid.eax, reg);
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+ }
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+ case MSR_FEATURE_WORD:
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+ return g_strdup_printf("MSR(%02XH)",
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+ f->msr.index);
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+ }
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+
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+ return NULL;
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+}
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+
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static void report_unavailable_features(FeatureWord w, uint32_t mask)
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{
|
|
FeatureWordInfo *f = &feature_word_info[w];
|
|
int i;
|
|
+ char *feat_word_str;
|
|
|
|
for (i = 0; i < 32; ++i) {
|
|
if ((1UL << i) & mask) {
|
|
- const char *reg = get_register_name_32(f->cpuid_reg);
|
|
- assert(reg);
|
|
- warn_report("%s doesn't support requested feature: "
|
|
- "CPUID.%02XH:%s%s%s [bit %d]",
|
|
+ feat_word_str = feature_word_description(f, i);
|
|
+ warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
|
|
accel_uses_host_cpuid() ? "host" : "TCG",
|
|
- f->cpuid_eax, reg,
|
|
+ feat_word_str,
|
|
f->feat_names[i] ? "." : "",
|
|
f->feat_names[i] ? f->feat_names[i] : "", i);
|
|
+ g_free(feat_word_str);
|
|
}
|
|
}
|
|
}
|
|
@@ -3118,11 +3187,18 @@ static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
|
|
|
|
for (w = 0; w < FEATURE_WORDS; w++) {
|
|
FeatureWordInfo *wi = &feature_word_info[w];
|
|
+ /*
|
|
+ * We didn't have MSR features when "feature-words" was
|
|
+ * introduced. Therefore skipped other type entries.
|
|
+ */
|
|
+ if (wi->type != CPUID_FEATURE_WORD) {
|
|
+ continue;
|
|
+ }
|
|
X86CPUFeatureWordInfo *qwi = &word_infos[w];
|
|
- qwi->cpuid_input_eax = wi->cpuid_eax;
|
|
- qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
|
|
- qwi->cpuid_input_ecx = wi->cpuid_ecx;
|
|
- qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
|
|
+ qwi->cpuid_input_eax = wi->cpuid.eax;
|
|
+ qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
|
|
+ qwi->cpuid_input_ecx = wi->cpuid.ecx;
|
|
+ qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
|
|
qwi->features = array[w];
|
|
|
|
/* List will be in reverse order, but order shouldn't matter */
|
|
@@ -3495,16 +3571,26 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
|
|
bool migratable_only)
|
|
{
|
|
FeatureWordInfo *wi = &feature_word_info[w];
|
|
- uint32_t r;
|
|
+ uint32_t r = 0;
|
|
|
|
if (kvm_enabled()) {
|
|
- r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
|
|
- wi->cpuid_ecx,
|
|
- wi->cpuid_reg);
|
|
+ switch (wi->type) {
|
|
+ case CPUID_FEATURE_WORD:
|
|
+ r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
|
|
+ wi->cpuid.ecx,
|
|
+ wi->cpuid.reg);
|
|
+ break;
|
|
+ case MSR_FEATURE_WORD:
|
|
+ r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
|
|
+ break;
|
|
+ }
|
|
} else if (hvf_enabled()) {
|
|
- r = hvf_get_supported_cpuid(wi->cpuid_eax,
|
|
- wi->cpuid_ecx,
|
|
- wi->cpuid_reg);
|
|
+ if (wi->type != CPUID_FEATURE_WORD) {
|
|
+ return 0;
|
|
+ }
|
|
+ r = hvf_get_supported_cpuid(wi->cpuid.eax,
|
|
+ wi->cpuid.ecx,
|
|
+ wi->cpuid.reg);
|
|
} else if (tcg_enabled()) {
|
|
r = wi->tcg_features;
|
|
} else {
|
|
@@ -4568,9 +4654,10 @@ static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
|
|
{
|
|
CPUX86State *env = &cpu->env;
|
|
FeatureWordInfo *fi = &feature_word_info[w];
|
|
- uint32_t eax = fi->cpuid_eax;
|
|
+ uint32_t eax = fi->cpuid.eax;
|
|
uint32_t region = eax & 0xF0000000;
|
|
|
|
+ assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
|
|
if (!env->features[w]) {
|
|
return;
|
|
}
|
|
--
|
|
2.20.1
|
|
|