40 lines
1.7 KiB
Diff
40 lines
1.7 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Yang Zhong <yang.zhong@linux.intel.com>
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Date: Thu, 6 Apr 2023 02:40:41 -0400
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Subject: [PATCH] target/i386: Change wrong XFRM value in SGX CPUID leaf
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
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FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}. As a result,
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SGX enclaves only supported SSE and x87 feature (xfrm=0x3).
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Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
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Signed-off-by: Yang Zhong <yang.zhong@linux.intel.com>
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Reviewed-by: Yang Weijiang <weijiang.yang@intel.com>
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Reviewed-by: Kai Huang <kai.huang@intel.com>
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Message-Id: <20230406064041.420039-1-yang.zhong@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry-picked from commit 72497cff896fecf74306ed33626c30e43633cdd6)
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Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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---
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target/i386/cpu.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 6576287e5b..f083ff4335 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5718,8 +5718,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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} else {
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*eax &= env->features[FEAT_SGX_12_1_EAX];
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*ebx &= 0; /* ebx reserve */
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- *ecx &= env->features[FEAT_XSAVE_XSS_LO];
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- *edx &= env->features[FEAT_XSAVE_XSS_HI];
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+ *ecx &= env->features[FEAT_XSAVE_XCR0_LO];
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+ *edx &= env->features[FEAT_XSAVE_XCR0_HI];
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/* FP and SSE are always allowed regardless of XSAVE/XCR0. */
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*ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK;
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