31 lines
1.3 KiB
Diff
31 lines
1.3 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Sat, 25 May 2024 10:03:22 +0200
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Subject: [PATCH] target/i386: no single-step exception after MOV or POP SS
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Intel SDM 18.3.1.4 "If an occurrence of the MOV or POP instruction
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loads the SS register executes with EFLAGS.TF = 1, no single-step debug
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exception occurs following the MOV or POP instruction."
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit f0f0136abba688a6516647a79cc91e03fad6d5d7)
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Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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---
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target/i386/tcg/translate.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
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index c2c5e73b3f..a55df176c6 100644
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--- a/target/i386/tcg/translate.c
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+++ b/target/i386/tcg/translate.c
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@@ -2817,7 +2817,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
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if (recheck_tf) {
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gen_helper_rechecking_single_step(tcg_env);
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tcg_gen_exit_tb(NULL, 0);
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- } else if (s->flags & HF_TF_MASK) {
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+ } else if ((s->flags & HF_TF_MASK) && !inhibit) {
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gen_helper_single_step(tcg_env);
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} else if (jr &&
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/* give irqs a chance to happen */
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