113 lines
3.9 KiB
Diff
113 lines
3.9 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Wed, 20 Dec 2017 10:52:54 +0000
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Subject: [PATCH] x86/cpu/AMD: Add speculative control support for AMD
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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Add speculative control support for AMD processors. For AMD, speculative
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control is indicated as follows:
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CPUID EAX=0x00000007, ECX=0x00 return EDX[26] indicates support for
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both IBRS and IBPB.
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CPUID EAX=0x80000008, ECX=0x00 return EBX[12] indicates support for
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just IBPB.
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On AMD family 0x10, 0x12 and 0x16 processors where either of the above
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features are not supported, IBPB can be achieved by disabling
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indirect branch predictor support in MSR 0xc0011021[14] at boot.
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Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 8c3fc9e98177daee2281ed40e3d61f9cf4eee576)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/msr-index.h | 1 +
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arch/x86/kernel/cpu/amd.c | 39 ++++++++++++++++++++++++++++++++++++++
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3 files changed, 41 insertions(+)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index 44be8fd069bf..a97b327137aa 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -268,6 +268,7 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */
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+#define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
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#define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index 4e3438a00a50..954aad6c32f4 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -345,6 +345,7 @@
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#define MSR_F15H_NB_PERF_CTR 0xc0010241
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#define MSR_F15H_PTSC 0xc0010280
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#define MSR_F15H_IC_CFG 0xc0011021
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+#define MSR_F15H_IC_CFG_DIS_IND BIT_ULL(14)
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/* Fam 10h MSRs */
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#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index 99eef4a09fd9..42871c1a8da8 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -830,6 +830,45 @@ static void init_amd(struct cpuinfo_x86 *c)
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/* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
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if (!cpu_has(c, X86_FEATURE_XENPV))
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set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
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+
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+ /* AMD speculative control support */
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+ if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
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+ pr_info_once("FEATURE SPEC_CTRL Present\n");
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+ set_ibrs_supported();
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+ set_ibpb_supported();
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+ if (ibrs_inuse)
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+ sysctl_ibrs_enabled = 1;
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+ if (ibpb_inuse)
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+ sysctl_ibpb_enabled = 1;
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+ } else if (cpu_has(c, X86_FEATURE_IBPB)) {
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+ pr_info_once("FEATURE SPEC_CTRL Not Present\n");
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+ pr_info_once("FEATURE IBPB Present\n");
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+ set_ibpb_supported();
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+ if (ibpb_inuse)
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+ sysctl_ibpb_enabled = 1;
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+ } else {
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+ pr_info_once("FEATURE SPEC_CTRL Not Present\n");
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+ pr_info_once("FEATURE IBPB Not Present\n");
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+ /*
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+ * On AMD processors that do not support the speculative
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+ * control features, IBPB type support can be achieved by
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+ * disabling indirect branch predictor support.
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+ */
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+ if (!ibpb_disabled) {
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+ u64 val;
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+
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+ switch (c->x86) {
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+ case 0x10:
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+ case 0x12:
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+ case 0x16:
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+ pr_info_once("Disabling indirect branch predictor support\n");
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+ rdmsrl(MSR_F15H_IC_CFG, val);
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+ val |= MSR_F15H_IC_CFG_DIS_IND;
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+ wrmsrl(MSR_F15H_IC_CFG, val);
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+ break;
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+ }
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+ }
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+ }
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}
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#ifdef CONFIG_X86_32
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--
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2.14.2
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