131 lines
4.7 KiB
Diff
131 lines
4.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Andy Lutomirski <luto@kernel.org>
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Date: Mon, 4 Dec 2017 15:07:19 +0100
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Subject: [PATCH] x86/entry: Move SYSENTER_stack to the beginning of struct
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tss_struct
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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SYSENTER_stack should have reliable overflow detection, which
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means that it needs to be at the bottom of a page, not the top.
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Move it to the beginning of struct tss_struct and page-align it.
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Also add an assertion to make sure that the fixed hardware TSS
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doesn't cross a page boundary.
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Signed-off-by: Andy Lutomirski <luto@kernel.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Borislav Petkov <bpetkov@suse.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Rik van Riel <riel@redhat.com>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Link: https://lkml.kernel.org/r/20171204150605.881827433@linutronix.de
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 1a935bc3d4ea61556461a9e92a68ca3556232efd)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 57d6cfd9e7d015aabbed6d0b50e7d2525b3c86c2)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/processor.h | 21 ++++++++++++---------
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arch/x86/kernel/cpu/common.c | 21 +++++++++++++++++++++
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2 files changed, 33 insertions(+), 9 deletions(-)
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diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
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index 78123abdb046..55885465c3a7 100644
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--- a/arch/x86/include/asm/processor.h
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+++ b/arch/x86/include/asm/processor.h
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@@ -326,7 +326,16 @@ struct x86_hw_tss {
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struct tss_struct {
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/*
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- * The hardware state:
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+ * Space for the temporary SYSENTER stack, used for SYSENTER
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+ * and the entry trampoline as well.
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+ */
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+ unsigned long SYSENTER_stack_canary;
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+ unsigned long SYSENTER_stack[64];
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+
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+ /*
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+ * The fixed hardware portion. This must not cross a page boundary
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+ * at risk of violating the SDM's advice and potentially triggering
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+ * errata.
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*/
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struct x86_hw_tss x86_tss;
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@@ -337,15 +346,9 @@ struct tss_struct {
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* be within the limit.
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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+} __aligned(PAGE_SIZE);
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- /*
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- * Space for the temporary SYSENTER stack.
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- */
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- unsigned long SYSENTER_stack_canary;
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- unsigned long SYSENTER_stack[64];
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-} ____cacheline_aligned;
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-
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-DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
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+DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss);
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/*
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* sizeof(unsigned long) coming from an extra "long" at the end
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index e526d82b546c..e61eff11f562 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -487,6 +487,27 @@ static inline void setup_cpu_entry_area(int cpu)
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#endif
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__set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot);
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+
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+ /*
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+ * The Intel SDM says (Volume 3, 7.2.1):
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+ *
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+ * Avoid placing a page boundary in the part of the TSS that the
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+ * processor reads during a task switch (the first 104 bytes). The
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+ * processor may not correctly perform address translations if a
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+ * boundary occurs in this area. During a task switch, the processor
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+ * reads and writes into the first 104 bytes of each TSS (using
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+ * contiguous physical addresses beginning with the physical address
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+ * of the first byte of the TSS). So, after TSS access begins, if
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+ * part of the 104 bytes is not physically contiguous, the processor
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+ * will access incorrect information without generating a page-fault
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+ * exception.
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+ *
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+ * There are also a lot of errata involving the TSS spanning a page
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+ * boundary. Assert that we're not doing that.
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+ */
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+ BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^
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+ offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK);
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+
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}
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/* Load the original GDT from the per-cpu structure */
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--
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2.14.2
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