144 lines
5.0 KiB
Diff
144 lines
5.0 KiB
Diff
From c8bd55aa2deb4e7491561567e8e01b71ab61ffe4 Mon Sep 17 00:00:00 2001
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From: Peter Zijlstra <peterz@infradead.org>
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Date: Tue, 5 Dec 2017 13:34:53 +0100
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Subject: [PATCH 212/232] x86/mm: Clarify the whole ASID/kernel PCID/user PCID
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naming
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Ideally we'd also use sparse to enforce this separation so it becomes much
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more difficult to mess up.
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 0a126abd576ebc6403f063dbe20cf7416c9d9393)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 2ee6efc0f708e21cfd08471132ac2255fac54553)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 55 ++++++++++++++++++++++++++++++++---------
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1 file changed, 43 insertions(+), 12 deletions(-)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index 979e590648a5..7a04a1f1ca11 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -12,16 +12,33 @@
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#include <asm/pti.h>
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#include <asm/processor-flags.h>
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-static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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-{
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- /*
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- * Bump the generation count. This also serves as a full barrier
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- * that synchronizes with switch_mm(): callers are required to order
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- * their read of mm_cpumask after their writes to the paging
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- * structures.
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- */
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- return atomic64_inc_return(&mm->context.tlb_gen);
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-}
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+/*
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+ * The x86 feature is called PCID (Process Context IDentifier). It is similar
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+ * to what is traditionally called ASID on the RISC processors.
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+ *
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+ * We don't use the traditional ASID implementation, where each process/mm gets
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+ * its own ASID and flush/restart when we run out of ASID space.
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+ *
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+ * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
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+ * that came by on this CPU, allowing cheaper switch_mm between processes on
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+ * this CPU.
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+ *
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+ * We end up with different spaces for different things. To avoid confusion we
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+ * use different names for each of them:
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+ *
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+ * ASID - [0, TLB_NR_DYN_ASIDS-1]
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+ * the canonical identifier for an mm
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+ *
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+ * kPCID - [1, TLB_NR_DYN_ASIDS]
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+ * the value we write into the PCID part of CR3; corresponds to the
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+ * ASID+1, because PCID 0 is special.
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+ *
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+ * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
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+ * for KPTI each mm has two address spaces and thus needs two
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+ * PCID values, but we can still do with a single ASID denomination
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+ * for each mm. Corresponds to kPCID + 2048.
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+ *
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+ */
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/* There are 12 bits of space for ASIDS in CR3 */
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#define CR3_HW_ASID_BITS 12
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@@ -40,7 +57,7 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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/*
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* ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
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- * for them being zero-based. Another -1 is because ASID 0 is reserved for
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+ * for them being zero-based. Another -1 is because PCID 0 is reserved for
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* use by non-PCID-aware users.
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*/
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#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
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@@ -51,6 +68,9 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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*/
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#define TLB_NR_DYN_ASIDS 6
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+/*
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+ * Given @asid, compute kPCID
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+ */
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static inline u16 kern_pcid(u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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@@ -85,7 +105,7 @@ static inline u16 kern_pcid(u16 asid)
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}
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/*
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- * The user PCID is just the kernel one, plus the "switch bit".
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+ * Given @asid, compute uPCID
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*/
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static inline u16 user_pcid(u16 asid)
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{
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@@ -473,6 +493,17 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long a)
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void native_flush_tlb_others(const struct cpumask *cpumask,
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const struct flush_tlb_info *info);
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+static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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+{
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+ /*
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+ * Bump the generation count. This also serves as a full barrier
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+ * that synchronizes with switch_mm(): callers are required to order
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+ * their read of mm_cpumask after their writes to the paging
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+ * structures.
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+ */
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+ return atomic64_inc_return(&mm->context.tlb_gen);
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+}
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+
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static inline void arch_tlbbatch_add_mm(struct arch_tlbflush_unmap_batch *batch,
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struct mm_struct *mm)
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{
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--
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2.14.2
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