97 lines
3.3 KiB
Diff
97 lines
3.3 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Mon, 4 Dec 2017 15:07:58 +0100
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Subject: [PATCH] x86/mm: Abstract switching CR3
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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In preparation to adding additional PCID flushing, abstract the
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loading of a new ASID into CR3.
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[ PeterZ: Split out from big combo patch ]
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 48e111982cda033fec832c6b0592c2acedd85d04)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 1e2affe2a79305b3a5f3ad65d3f61ad9d1f9e168)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/mm/tlb.c | 22 ++++++++++++++++++++--
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1 file changed, 20 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
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index ce87b69fb4e0..353f2f4e1d96 100644
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--- a/arch/x86/mm/tlb.c
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+++ b/arch/x86/mm/tlb.c
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@@ -101,6 +101,24 @@ static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
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*need_flush = true;
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}
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+static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
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+{
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+ unsigned long new_mm_cr3;
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+
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+ if (need_flush) {
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+ new_mm_cr3 = build_cr3(pgdir, new_asid);
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+ } else {
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+ new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
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+ }
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+
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+ /*
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+ * Caution: many callers of this function expect
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+ * that load_cr3() is serializing and orders TLB
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+ * fills with respect to the mm_cpumask writes.
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+ */
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+ write_cr3(new_mm_cr3);
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+}
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+
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void leave_mm(int cpu)
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{
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struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
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@@ -228,7 +246,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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if (need_flush) {
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
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- write_cr3(build_cr3(next->pgd, new_asid));
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+ load_new_mm_cr3(next->pgd, new_asid, true);
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/*
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* NB: This gets called via leave_mm() in the idle path
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@@ -241,7 +259,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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} else {
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/* The new ASID is already up to date. */
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- write_cr3(build_cr3_noflush(next->pgd, new_asid));
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+ load_new_mm_cr3(next->pgd, new_asid, false);
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/* See above wrt _rcuidle. */
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trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
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--
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2.14.2
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