110 lines
4.0 KiB
Diff
110 lines
4.0 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Mon, 4 Dec 2017 15:07:56 +0100
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Subject: [PATCH] x86/mm: Put MMU to hardware ASID translation in one place
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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There are effectively two ASID types:
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1. The one stored in the mmu_context that goes from 0..5
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2. The one programmed into the hardware that goes from 1..6
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This consolidates the locations where converting between the two (by doing
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a +1) to a single place which gives us a nice place to comment.
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PAGE_TABLE_ISOLATION will also need to, given an ASID, know which hardware
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ASID to flush for the userspace mapping.
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit dd95f1a4b5ca904c78e6a097091eb21436478abb)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 6f3e88a8f41123ac339d28cfdda5da0e85bec550)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 31 +++++++++++++++++++------------
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1 file changed, 19 insertions(+), 12 deletions(-)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index c1c10db4156c..ecd634f87e4e 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -84,30 +84,37 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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*/
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#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)
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-/*
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- * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.
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- * This serves two purposes. It prevents a nasty situation in which
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- * PCID-unaware code saves CR3, loads some other value (with PCID == 0),
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- * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved
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- * ASID was nonzero. It also means that any bugs involving loading a
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- * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically.
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- */
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+static inline u16 kern_pcid(u16 asid)
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+{
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+ VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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+ /*
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+ * If PCID is on, ASID-aware code paths put the ASID+1 into the
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+ * PCID bits. This serves two purposes. It prevents a nasty
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+ * situation in which PCID-unaware code saves CR3, loads some other
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+ * value (with PCID == 0), and then restores CR3, thus corrupting
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+ * the TLB for ASID 0 if the saved ASID was nonzero. It also means
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+ * that any bugs involving loading a PCID-enabled CR3 with
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+ * CR4.PCIDE off will trigger deterministically.
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+ */
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+ return asid + 1;
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+}
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+
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struct pgd_t;
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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{
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if (static_cpu_has(X86_FEATURE_PCID)) {
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- VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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- return __sme_pa(pgd) | (asid + 1);
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+ return __pa(pgd) | kern_pcid(asid);
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} else {
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VM_WARN_ON_ONCE(asid != 0);
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- return __sme_pa(pgd);
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+ return __pa(pgd);
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}
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}
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static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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{
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VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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- return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
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+ VM_WARN_ON_ONCE(!this_cpu_has(X86_FEATURE_PCID));
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+ return __pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
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}
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#ifdef CONFIG_PARAVIRT
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--
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2.14.2
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