110 lines
3.5 KiB
Diff
110 lines
3.5 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Andi Kleen <ak@linux.intel.com>
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Date: Thu, 31 Aug 2017 14:46:30 -0700
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Subject: [PATCH] perf/x86: Enable free running PEBS for REGS_USER/INTR
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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[ Note, this is a Git cherry-pick of the following commit:
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a47ba4d77e12 ("perf/x86: Enable free running PEBS for REGS_USER/INTR")
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... for easier x86 PTI code testing and back-porting. ]
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Currently free running PEBS is disabled when user or interrupt
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registers are requested. Most of the registers are actually
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available in the PEBS record and can be supported.
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So we just need to check for the supported registers and then
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allow it: it is all except for the segment register.
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For user registers this only works when the counter is limited
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to ring 3 only, so this also needs to be checked.
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Signed-off-by: Andi Kleen <ak@linux.intel.com>
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Thomas Gleixner <tglx@linutronix.de>
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Link: http://lkml.kernel.org/r/20170831214630.21892-1-andi@firstfloor.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(backported from commit 2fe1bc1f501d55e5925b4035bcd85781adc76c63)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 06c6715f5b78b9976e72467b6bba510e243e5aad)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/events/perf_event.h | 24 +++++++++++++++++++++++-
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arch/x86/events/intel/core.c | 4 ++++
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2 files changed, 27 insertions(+), 1 deletion(-)
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diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
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index 0f7dad8bd358..590eaf7c2c3e 100644
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--- a/arch/x86/events/perf_event.h
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+++ b/arch/x86/events/perf_event.h
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@@ -85,13 +85,15 @@ struct amd_nb {
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* Flags PEBS can handle without an PMI.
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*
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* TID can only be handled by flushing at context switch.
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+ * REGS_USER can be handled for events limited to ring 3.
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*
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*/
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#define PEBS_FREERUNNING_FLAGS \
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(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
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PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
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PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
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- PERF_SAMPLE_TRANSACTION)
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+ PERF_SAMPLE_TRANSACTION | \
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+ PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
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/*
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* A debug store configuration.
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@@ -110,6 +112,26 @@ struct debug_store {
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u64 pebs_event_reset[MAX_PEBS_EVENTS];
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};
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+#define PEBS_REGS \
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+ (PERF_REG_X86_AX | \
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+ PERF_REG_X86_BX | \
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+ PERF_REG_X86_CX | \
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+ PERF_REG_X86_DX | \
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+ PERF_REG_X86_DI | \
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+ PERF_REG_X86_SI | \
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+ PERF_REG_X86_SP | \
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+ PERF_REG_X86_BP | \
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+ PERF_REG_X86_IP | \
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+ PERF_REG_X86_FLAGS | \
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+ PERF_REG_X86_R8 | \
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+ PERF_REG_X86_R9 | \
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+ PERF_REG_X86_R10 | \
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+ PERF_REG_X86_R11 | \
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+ PERF_REG_X86_R12 | \
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+ PERF_REG_X86_R13 | \
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+ PERF_REG_X86_R14 | \
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+ PERF_REG_X86_R15)
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+
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/*
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* Per register state.
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*/
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diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
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index 6f342001ec6a..7f3afbf928bb 100644
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--- a/arch/x86/events/intel/core.c
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+++ b/arch/x86/events/intel/core.c
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@@ -2958,6 +2958,10 @@ static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
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if (event->attr.use_clockid)
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flags &= ~PERF_SAMPLE_TIME;
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+ if (!event->attr.exclude_kernel)
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+ flags &= ~PERF_SAMPLE_REGS_USER;
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+ if (event->attr.sample_regs_user & ~PEBS_REGS)
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+ flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
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return flags;
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}
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--
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2.14.2
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