89 lines
3.6 KiB
Diff
89 lines
3.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
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Date: Sun, 5 Nov 2017 18:27:51 -0800
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Subject: [PATCH] x86/cpufeature: Add User-Mode Instruction Prevention
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definitions
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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[ Note, this is a Git cherry-pick of the following commit: (limited to the cpufeatures.h file)
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3522c2a6a4f3 ("x86/cpufeature: Add User-Mode Instruction Prevention definitions")
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... for easier x86 PTI code testing and back-porting. ]
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User-Mode Instruction Prevention is a security feature present in new
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Intel processors that, when set, prevents the execution of a subset of
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instructions if such instructions are executed in user mode (CPL > 0).
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Attempting to execute such instructions causes a general protection
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exception.
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The subset of instructions comprises:
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* SGDT - Store Global Descriptor Table
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* SIDT - Store Interrupt Descriptor Table
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* SLDT - Store Local Descriptor Table
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* SMSW - Store Machine Status Word
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* STR - Store Task Register
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This feature is also added to the list of disabled-features to allow
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a cleaner handling of build-time configuration.
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Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
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Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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Reviewed-by: Borislav Petkov <bp@suse.de>
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Cc: Andrew Morton <akpm@linux-foundation.org>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Chen Yucong <slaoub@gmail.com>
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Cc: Chris Metcalf <cmetcalf@mellanox.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Fenghua Yu <fenghua.yu@intel.com>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Huang Rui <ray.huang@amd.com>
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Cc: Jiri Slaby <jslaby@suse.cz>
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Cc: Jonathan Corbet <corbet@lwn.net>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Masami Hiramatsu <mhiramat@kernel.org>
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Cc: Michael S. Tsirkin <mst@redhat.com>
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Cc: Paolo Bonzini <pbonzini@redhat.com>
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Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
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Cc: Shuah Khan <shuah@kernel.org>
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Cc: Tony Luck <tony.luck@intel.com>
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Cc: Vlastimil Babka <vbabka@suse.cz>
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Cc: ricardo.neri@intel.com
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Link: http://lkml.kernel.org/r/1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit a8b4db562e7283a1520f9e9730297ecaab7622ea)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 6193ddb9de38665ba45f7f17dd9713baec3673ca)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index 6db782ed9cdb..0ea630bb3e74 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -295,6 +295,7 @@
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/* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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+#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
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#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
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--
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2.14.2
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