59d5af6732
drop numbers and commit hashes from patch metadata to reduce future patch churn
87 lines
4.1 KiB
Diff
87 lines
4.1 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Gayatri Kammela <gayatri.kammela@intel.com>
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Date: Mon, 30 Oct 2017 18:20:29 -0700
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Subject: [PATCH] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
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in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
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AVX512_BITALG.
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CPUID.(EAX=7,ECX=0):ECX[bit 6] AVX512_VBMI2
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CPUID.(EAX=7,ECX=0):ECX[bit 8] GFNI
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CPUID.(EAX=7,ECX=0):ECX[bit 9] VAES
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CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
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CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
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CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
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Detailed information of CPUID bits for these features can be found
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in the Intel Architecture Instruction Set Extensions and Future Features
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Programming Interface document (refer to Table 1-1. and Table 1-2.).
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A copy of this document is available at
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https://bugzilla.kernel.org/show_bug.cgi?id=197239
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Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
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Acked-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andi Kleen <andi.kleen@intel.com>
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Cc: Fenghua Yu <fenghua.yu@intel.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Ravi Shankar <ravi.v.shankar@intel.com>
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Cc: Ricardo Neri <ricardo.neri@intel.com>
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Cc: Yang Zhong <yang.zhong@intel.com>
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Cc: bp@alien8.de
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Link: http://lkml.kernel.org/r/1509412829-23380-1-git-send-email-gayatri.kammela@intel.com
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit c128dbfa0f879f8ce7b79054037889b0b2240728)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit b29eb29c5aca4708d66fa977db40c779366636a2)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 6 ++++++
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arch/x86/kernel/cpu/cpuid-deps.c | 6 ++++++
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2 files changed, 12 insertions(+)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index f4e145c4b06f..c465bd6613ed 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -297,6 +297,12 @@
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#define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
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#define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */
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#define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */
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+#define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
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+#define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */
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+#define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */
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+#define X86_FEATURE_VPCLMULQDQ (16*32+ 10) /* Carry-Less Multiplication Double Quadword */
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+#define X86_FEATURE_AVX512_VNNI (16*32+ 11) /* Vector Neural Network Instructions */
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+#define X86_FEATURE_AVX512_BITALG (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB */
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#define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */
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#define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */
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#define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */
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diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c
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index c1d49842a411..c21f22d836ad 100644
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--- a/arch/x86/kernel/cpu/cpuid-deps.c
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+++ b/arch/x86/kernel/cpu/cpuid-deps.c
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@@ -50,6 +50,12 @@ const static struct cpuid_dep cpuid_deps[] = {
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{ X86_FEATURE_AVX512BW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VL, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512VBMI, X86_FEATURE_AVX512F },
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+ { X86_FEATURE_AVX512_VBMI2, X86_FEATURE_AVX512VL },
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+ { X86_FEATURE_GFNI, X86_FEATURE_AVX512VL },
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+ { X86_FEATURE_VAES, X86_FEATURE_AVX512VL },
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+ { X86_FEATURE_VPCLMULQDQ, X86_FEATURE_AVX512VL },
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+ { X86_FEATURE_AVX512_VNNI, X86_FEATURE_AVX512VL },
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+ { X86_FEATURE_AVX512_BITALG, X86_FEATURE_AVX512VL },
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{ X86_FEATURE_AVX512_4VNNIW, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_4FMAPS, X86_FEATURE_AVX512F },
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{ X86_FEATURE_AVX512_VPOPCNTDQ, X86_FEATURE_AVX512F },
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--
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2.14.2
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