195 lines
6.6 KiB
Diff
195 lines
6.6 KiB
Diff
From 534c2338c3f72069910c06eba7693a4a1d15faf8 Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Mon, 4 Dec 2017 15:08:01 +0100
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Subject: [PATCH 211/231] x86/mm: Use INVPCID for __native_flush_tlb_single()
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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This uses INVPCID to shoot down individual lines of the user mapping
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instead of marking the entire user map as invalid. This
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could/might/possibly be faster.
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This for sure needs tlb_single_page_flush_ceiling to be redetermined;
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esp. since INVPCID is _slow_.
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A detailed performance analysis is available here:
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https://lkml.kernel.org/r/3062e486-3539-8a1f-5724-16199420be71@intel.com
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[ Peterz: Split out from big combo patch ]
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 6cff64b86aaaa07f89f50498055a20e45754b0c1)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit e4986a4e89c0eb40f824a8505feefff3328ad4b2)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/tlbflush.h | 23 +++++++++++++-
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arch/x86/mm/init.c | 64 ++++++++++++++++++++++----------------
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3 files changed, 60 insertions(+), 28 deletions(-)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index de4e91452de4..9b0c283afcf0 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -196,6 +196,7 @@
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#define X86_FEATURE_CAT_L3 ( 7*32+ 4) /* Cache Allocation Technology L3 */
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#define X86_FEATURE_CAT_L2 ( 7*32+ 5) /* Cache Allocation Technology L2 */
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#define X86_FEATURE_CDP_L3 ( 7*32+ 6) /* Code and Data Prioritization L3 */
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+#define X86_FEATURE_INVPCID_SINGLE ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index 2b7b32c243f1..979e590648a5 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -84,6 +84,18 @@ static inline u16 kern_pcid(u16 asid)
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return asid + 1;
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}
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+/*
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+ * The user PCID is just the kernel one, plus the "switch bit".
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+ */
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+static inline u16 user_pcid(u16 asid)
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+{
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+ u16 ret = kern_pcid(asid);
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+#ifdef CONFIG_PAGE_TABLE_ISOLATION
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+ ret |= 1 << X86_CR3_PTI_SWITCH_BIT;
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+#endif
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+ return ret;
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+}
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+
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struct pgd_t;
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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{
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@@ -324,6 +336,8 @@ static inline void __native_flush_tlb_global(void)
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/*
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* Using INVPCID is considerably faster than a pair of writes
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* to CR4 sandwiched inside an IRQ flag save/restore.
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+ *
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+ * Note, this works with CR4.PCIDE=0 or 1.
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*/
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invpcid_flush_all();
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return;
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@@ -357,7 +371,14 @@ static inline void __native_flush_tlb_single(unsigned long addr)
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if (!static_cpu_has(X86_FEATURE_PTI))
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return;
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- invalidate_user_asid(loaded_mm_asid);
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+ /*
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+ * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
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+ * Just use invalidate_user_asid() in case we are called early.
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+ */
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+ if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
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+ invalidate_user_asid(loaded_mm_asid);
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+ else
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+ invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
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}
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/*
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diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
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index caeb8a7bf0a4..80259ad8c386 100644
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--- a/arch/x86/mm/init.c
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+++ b/arch/x86/mm/init.c
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@@ -203,34 +203,44 @@ static void __init probe_page_size_mask(void)
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static void setup_pcid(void)
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{
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-#ifdef CONFIG_X86_64
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- if (boot_cpu_has(X86_FEATURE_PCID)) {
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- if (boot_cpu_has(X86_FEATURE_PGE)) {
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- /*
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- * This can't be cr4_set_bits_and_update_boot() --
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- * the trampoline code can't handle CR4.PCIDE and
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- * it wouldn't do any good anyway. Despite the name,
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- * cr4_set_bits_and_update_boot() doesn't actually
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- * cause the bits in question to remain set all the
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- * way through the secondary boot asm.
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- *
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- * Instead, we brute-force it and set CR4.PCIDE
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- * manually in start_secondary().
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- */
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- cr4_set_bits(X86_CR4_PCIDE);
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- } else {
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- /*
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- * flush_tlb_all(), as currently implemented, won't
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- * work if PCID is on but PGE is not. Since that
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- * combination doesn't exist on real hardware, there's
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- * no reason to try to fully support it, but it's
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- * polite to avoid corrupting data if we're on
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- * an improperly configured VM.
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- */
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- setup_clear_cpu_cap(X86_FEATURE_PCID);
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- }
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+ if (!IS_ENABLED(CONFIG_X86_64))
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+ return;
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+
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+ if (!boot_cpu_has(X86_FEATURE_PCID))
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+ return;
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+
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+ if (boot_cpu_has(X86_FEATURE_PGE)) {
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+ /*
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+ * This can't be cr4_set_bits_and_update_boot() -- the
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+ * trampoline code can't handle CR4.PCIDE and it wouldn't
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+ * do any good anyway. Despite the name,
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+ * cr4_set_bits_and_update_boot() doesn't actually cause
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+ * the bits in question to remain set all the way through
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+ * the secondary boot asm.
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+ *
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+ * Instead, we brute-force it and set CR4.PCIDE manually in
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+ * start_secondary().
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+ */
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+ cr4_set_bits(X86_CR4_PCIDE);
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+
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+ /*
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+ * INVPCID's single-context modes (2/3) only work if we set
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+ * X86_CR4_PCIDE, *and* we INVPCID support. It's unusable
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+ * on systems that have X86_CR4_PCIDE clear, or that have
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+ * no INVPCID support at all.
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+ */
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+ if (boot_cpu_has(X86_FEATURE_INVPCID))
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+ setup_force_cpu_cap(X86_FEATURE_INVPCID_SINGLE);
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+ } else {
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+ /*
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+ * flush_tlb_all(), as currently implemented, won't work if
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+ * PCID is on but PGE is not. Since that combination
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+ * doesn't exist on real hardware, there's no reason to try
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+ * to fully support it, but it's polite to avoid corrupting
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+ * data if we're on an improperly configured VM.
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+ */
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+ setup_clear_cpu_cap(X86_FEATURE_PCID);
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}
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-#endif
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}
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#ifdef CONFIG_X86_32
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--
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2.14.2
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