321d628a98
picked from Ubuntu-4.13.0-23.26
121 lines
4.5 KiB
Diff
121 lines
4.5 KiB
Diff
From 05be4302d695b8676c90b26abe0495df58602685 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Mon, 4 Dec 2017 15:07:33 +0100
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Subject: [PATCH 187/231] x86/cpufeatures: Add X86_BUG_CPU_INSECURE
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Many x86 CPUs leak information to user space due to missing isolation of
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user space and kernel space page tables. There are many well documented
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ways to exploit that.
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The upcoming software migitation of isolating the user and kernel space
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page tables needs a misfeature flag so code can be made runtime
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conditional.
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Add the BUG bits which indicates that the CPU is affected and add a feature
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bit which indicates that the software migitation is enabled.
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Assume for now that _ALL_ x86 CPUs are affected by this. Exceptions can be
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made later.
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit a89f040fa34ec9cd682aed98b8f04e3c47d998bd)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 3b0dffb3557f6a1084a2b92ac0cc2d36b5e1f39f)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 3 ++-
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arch/x86/include/asm/disabled-features.h | 8 +++++++-
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arch/x86/kernel/cpu/common.c | 4 ++++
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3 files changed, 13 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index d57a174ec97c..de4e91452de4 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -200,7 +200,7 @@
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#define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* AMD HW-PState */
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#define X86_FEATURE_PROC_FEEDBACK ( 7*32+ 9) /* AMD ProcFeedbackInterface */
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#define X86_FEATURE_SME ( 7*32+10) /* AMD Secure Memory Encryption */
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-
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+#define X86_FEATURE_PTI ( 7*32+11) /* Kernel Page Table Isolation enabled */
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#define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */
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#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
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#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network Instructions */
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@@ -339,5 +339,6 @@
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#define X86_BUG_SWAPGS_FENCE X86_BUG(11) /* SWAPGS without input dep on GS */
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#define X86_BUG_MONITOR X86_BUG(12) /* IPI required to wake up remote CPU */
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#define X86_BUG_AMD_E400 X86_BUG(13) /* CPU is among the affected by Erratum 400 */
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+#define X86_BUG_CPU_INSECURE X86_BUG(14) /* CPU is insecure and needs kernel page table isolation */
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#endif /* _ASM_X86_CPUFEATURES_H */
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diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
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index 5dff775af7cd..db681152f024 100644
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--- a/arch/x86/include/asm/disabled-features.h
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+++ b/arch/x86/include/asm/disabled-features.h
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@@ -42,6 +42,12 @@
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# define DISABLE_LA57 (1<<(X86_FEATURE_LA57 & 31))
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#endif
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+#ifdef CONFIG_PAGE_TABLE_ISOLATION
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+# define DISABLE_PTI 0
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+#else
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+# define DISABLE_PTI (1 << (X86_FEATURE_PTI & 31))
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+#endif
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+
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/*
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* Make sure to add features to the correct mask
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*/
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@@ -52,7 +58,7 @@
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#define DISABLED_MASK4 0
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#define DISABLED_MASK5 0
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#define DISABLED_MASK6 0
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-#define DISABLED_MASK7 0
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+#define DISABLED_MASK7 (DISABLE_PTI)
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#define DISABLED_MASK8 0
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#define DISABLED_MASK9 (DISABLE_MPX)
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#define DISABLED_MASK10 0
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 96171ce46d61..623ba3635793 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -898,6 +898,10 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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}
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setup_force_cpu_cap(X86_FEATURE_ALWAYS);
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+
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+ /* Assume for now that ALL x86 CPUs are insecure */
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+ setup_force_cpu_bug(X86_BUG_CPU_INSECURE);
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+
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fpu__init_system(c);
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}
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--
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2.14.2
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