97 lines
3.4 KiB
Diff
97 lines
3.4 KiB
Diff
From f847420cd768a0b95c3159ab822c30c909f0e5ee Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Mon, 4 Dec 2017 15:07:55 +0100
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Subject: [PATCH 180/231] x86/mm: Remove hard-coded ASID limit checks
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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First, it's nice to remove the magic numbers.
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Second, PAGE_TABLE_ISOLATION is going to consume half of the available ASID
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space. The space is currently unused, but add a comment to spell out this
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new restriction.
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit cb0a9144a744e55207e24dcef812f05cd15a499a)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit fd5d001ae73ccd382d4270f53e27dcf61c4e4749)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 20 ++++++++++++++++++--
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1 file changed, 18 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index 3a421b164868..c1c10db4156c 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -68,6 +68,22 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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return atomic64_inc_return(&mm->context.tlb_gen);
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}
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+/* There are 12 bits of space for ASIDS in CR3 */
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+#define CR3_HW_ASID_BITS 12
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+/*
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+ * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
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+ * user/kernel switches
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+ */
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+#define PTI_CONSUMED_ASID_BITS 0
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+
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+#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS - PTI_CONSUMED_ASID_BITS)
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+/*
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+ * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
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+ * for them being zero-based. Another -1 is because ASID 0 is reserved for
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+ * use by non-PCID-aware users.
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+ */
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+#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_ASID_BITS) - 2)
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+
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/*
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* If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.
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* This serves two purposes. It prevents a nasty situation in which
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@@ -80,7 +96,7 @@ struct pgd_t;
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static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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{
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if (static_cpu_has(X86_FEATURE_PCID)) {
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- VM_WARN_ON_ONCE(asid > 4094);
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+ VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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return __sme_pa(pgd) | (asid + 1);
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} else {
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VM_WARN_ON_ONCE(asid != 0);
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@@ -90,7 +106,7 @@ static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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{
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- VM_WARN_ON_ONCE(asid > 4094);
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+ VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
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return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
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}
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--
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2.14.2
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