114 lines
3.2 KiB
Diff
114 lines
3.2 KiB
Diff
From 0e75b184111dbcd07911712bd87991df186c5fd3 Mon Sep 17 00:00:00 2001
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From: Peter Zijlstra <peterz@infradead.org>
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Date: Tue, 5 Dec 2017 13:34:52 +0100
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Subject: [PATCH 178/231] x86/mm: Add comments to clarify which TLB-flush
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functions are supposed to flush what
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Per popular request..
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(backported from commit 3f67af51e56f291d7417d77c4f67cd774633c5e1)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 8394b666c2b3b1fc5279a897c96b196531923f3b)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 24 ++++++++++++++++++++++--
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1 file changed, 22 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index bc1460b4737b..ed5d483c4a1b 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -216,6 +216,10 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
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cr4_set_bits(mask);
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}
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+
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+/*
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+ * flush the entire current user mapping
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+ */
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static inline void __native_flush_tlb(void)
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{
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/*
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@@ -228,6 +232,9 @@ static inline void __native_flush_tlb(void)
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preempt_enable();
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}
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+/*
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+ * flush everything
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+ */
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static inline void __native_flush_tlb_global(void)
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{
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unsigned long cr4, flags;
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@@ -257,17 +264,27 @@ static inline void __native_flush_tlb_global(void)
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raw_local_irq_restore(flags);
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}
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+/*
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+ * flush one page in the user mapping
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+ */
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static inline void __native_flush_tlb_single(unsigned long addr)
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{
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asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
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}
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+/*
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+ * flush everything
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+ */
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static inline void __flush_tlb_all(void)
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{
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- if (boot_cpu_has(X86_FEATURE_PGE))
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+ if (boot_cpu_has(X86_FEATURE_PGE)) {
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__flush_tlb_global();
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- else
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+ } else {
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+ /*
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+ * !PGE -> !PCID (setup_pcid()), thus every flush is total.
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+ */
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__flush_tlb();
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+ }
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/*
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* Note: if we somehow had PCID but not PGE, then this wouldn't work --
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@@ -278,6 +295,9 @@ static inline void __flush_tlb_all(void)
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*/
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}
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+/*
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+ * flush one page in the kernel mapping
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+ */
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static inline void __flush_tlb_one(unsigned long addr)
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{
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count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
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--
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2.14.2
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