127 lines
3.9 KiB
Diff
127 lines
3.9 KiB
Diff
From e80edf9b45a0465ce8fbded75f6d5f218039a67c Mon Sep 17 00:00:00 2001
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From: Peter Zijlstra <peterz@infradead.org>
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Date: Tue, 5 Dec 2017 13:34:51 +0100
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Subject: [PATCH 175/231] x86/microcode: Dont abuse the TLB-flush interface
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Commit:
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ec400ddeff20 ("x86/microcode_intel_early.c: Early update ucode on Intel's CPU")
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... grubbed into tlbflush internals without coherent explanation.
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Since it says its a precaution and the SDM doesn't mention anything like
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this, take it out back.
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Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: Dave Hansen <dave.hansen@linux.intel.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: fenghua.yu@intel.com
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 23cb7d46f371844c004784ad9552a57446f73e5a)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 0f3d96d1e5aa4d9538ab1a918fb49f2c57ebb6f5)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 19 ++++++-------------
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arch/x86/kernel/cpu/microcode/intel.c | 13 -------------
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2 files changed, 6 insertions(+), 26 deletions(-)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index 6533da3036c9..6d2688a6fda0 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -234,20 +234,9 @@ static inline void __native_flush_tlb(void)
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preempt_enable();
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}
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-static inline void __native_flush_tlb_global_irq_disabled(void)
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-{
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- unsigned long cr4;
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-
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- cr4 = this_cpu_read(cpu_tlbstate.cr4);
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- /* clear PGE */
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- native_write_cr4(cr4 & ~X86_CR4_PGE);
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- /* write old PGE again and flush TLBs */
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- native_write_cr4(cr4);
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-}
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-
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static inline void __native_flush_tlb_global(void)
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{
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- unsigned long flags;
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+ unsigned long cr4, flags;
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if (static_cpu_has(X86_FEATURE_INVPCID)) {
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/*
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@@ -265,7 +254,11 @@ static inline void __native_flush_tlb_global(void)
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*/
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raw_local_irq_save(flags);
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- __native_flush_tlb_global_irq_disabled();
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+ cr4 = this_cpu_read(cpu_tlbstate.cr4);
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+ /* toggle PGE */
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+ native_write_cr4(cr4 ^ X86_CR4_PGE);
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+ /* write old PGE again and flush TLBs */
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+ native_write_cr4(cr4);
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raw_local_irq_restore(flags);
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}
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diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
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index 636a5fcfdeb7..d9a8f69101aa 100644
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--- a/arch/x86/kernel/cpu/microcode/intel.c
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+++ b/arch/x86/kernel/cpu/microcode/intel.c
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@@ -564,15 +564,6 @@ static void print_ucode(struct ucode_cpu_info *uci)
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}
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#else
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-/*
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- * Flush global tlb. We only do this in x86_64 where paging has been enabled
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- * already and PGE should be enabled as well.
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- */
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-static inline void flush_tlb_early(void)
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-{
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- __native_flush_tlb_global_irq_disabled();
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-}
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-
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static inline void print_ucode(struct ucode_cpu_info *uci)
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{
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struct microcode_intel *mc;
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@@ -601,10 +592,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
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if (rev != mc->hdr.rev)
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return -1;
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-#ifdef CONFIG_X86_64
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- /* Flush global tlb. This is precaution. */
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- flush_tlb_early();
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-#endif
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uci->cpu_sig.rev = rev;
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if (early)
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--
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2.14.2
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