87 lines
3.4 KiB
Diff
87 lines
3.4 KiB
Diff
From b5143e55b3bf018b3ad2598e677ceb5e155eba6f Mon Sep 17 00:00:00 2001
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From: Andy Lutomirski <luto@kernel.org>
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Date: Sun, 17 Sep 2017 09:03:49 -0700
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Subject: [PATCH 044/231] x86/mm/64: Stop using CR3.PCID == 0 in ASID-aware
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code
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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Putting the logical ASID into CR3's PCID bits directly means that we
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have two cases to consider separately: ASID == 0 and ASID != 0.
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This means that bugs that only hit in one of these cases trigger
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nondeterministically.
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There were some bugs like this in the past, and I think there's
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still one in current kernels. In particular, we have a number of
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ASID-unware code paths that save CR3, write some special value, and
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then restore CR3. This includes suspend/resume, hibernate, kexec,
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EFI, and maybe other things I've missed. This is currently
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dangerous: if ASID != 0, then this code sequence will leave garbage
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in the TLB tagged for ASID 0. We could potentially see corruption
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when switching back to ASID 0. In principle, an
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initialize_tlbstate_and_flush() call after these sequences would
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solve the problem, but EFI, at least, does not call this. (And it
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probably shouldn't -- initialize_tlbstate_and_flush() is rather
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expensive.)
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Signed-off-by: Andy Lutomirski <luto@kernel.org>
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Cc: Borislav Petkov <bpetkov@suse.de>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Thomas Gleixner <tglx@linutronix.de>
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Link: http://lkml.kernel.org/r/cdc14bbe5d3c3ef2a562be09a6368ffe9bd947a6.1505663533.git.luto@kernel.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 52a2af400c1075219b3f0ce5c96fc961da44018a)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 15e474753e66e44da1365049f465427053a453ba)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/mmu_context.h | 21 +++++++++++++++++++--
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1 file changed, 19 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
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index a999ba6b721f..c120b5db178a 100644
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--- a/arch/x86/include/asm/mmu_context.h
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+++ b/arch/x86/include/asm/mmu_context.h
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@@ -286,14 +286,31 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
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return __pkru_allows_pkey(vma_pkey(vma), write);
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}
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+/*
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+ * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
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+ * bits. This serves two purposes. It prevents a nasty situation in
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+ * which PCID-unaware code saves CR3, loads some other value (with PCID
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+ * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
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+ * the saved ASID was nonzero. It also means that any bugs involving
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+ * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
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+ * deterministically.
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+ */
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+
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static inline unsigned long build_cr3(struct mm_struct *mm, u16 asid)
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{
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- return __sme_pa(mm->pgd) | asid;
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+ if (static_cpu_has(X86_FEATURE_PCID)) {
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+ VM_WARN_ON_ONCE(asid > 4094);
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+ return __sme_pa(mm->pgd) | (asid + 1);
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+ } else {
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+ VM_WARN_ON_ONCE(asid != 0);
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+ return __sme_pa(mm->pgd);
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+ }
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}
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static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid)
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{
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- return __sme_pa(mm->pgd) | asid | CR3_NOFLUSH;
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+ VM_WARN_ON_ONCE(asid > 4094);
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+ return __sme_pa(mm->pgd) | (asid + 1) | CR3_NOFLUSH;
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}
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/*
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--
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2.14.2
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