238 lines
7.9 KiB
Diff
238 lines
7.9 KiB
Diff
From d9fd6653e5dd9d80c7c75065329250529281e02d Mon Sep 17 00:00:00 2001
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From: Andy Lutomirski <luto@kernel.org>
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Date: Sun, 10 Sep 2017 17:48:27 -0700
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Subject: [PATCH 032/231] x86/mm/64: Initialize CR4.PCIDE early
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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cpu_init() is weird: it's called rather late (after early
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identification and after most MMU state is initialized) on the boot
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CPU but is called extremely early (before identification) on secondary
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CPUs. It's called just late enough on the boot CPU that its CR4 value
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isn't propagated to mmu_cr4_features.
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Even if we put CR4.PCIDE into mmu_cr4_features, we'd hit two
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problems. First, we'd crash in the trampoline code. That's
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fixable, and I tried that. It turns out that mmu_cr4_features is
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totally ignored by secondary_start_64(), though, so even with the
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trampoline code fixed, it wouldn't help.
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This means that we don't currently have CR4.PCIDE reliably initialized
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before we start playing with cpu_tlbstate. This is very fragile and
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tends to cause boot failures if I make even small changes to the TLB
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handling code.
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Make it more robust: initialize CR4.PCIDE earlier on the boot CPU
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and propagate it to secondary CPUs in start_secondary().
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( Yes, this is ugly. I think we should have improved mmu_cr4_features
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to actually control CR4 during secondary bootup, but that would be
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fairly intrusive at this stage. )
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Signed-off-by: Andy Lutomirski <luto@kernel.org>
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Reported-by: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
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Tested-by: Sai Praneeth Prakhya <sai.praneeth.prakhya@intel.com>
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Cc: Borislav Petkov <bpetkov@suse.de>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Thomas Gleixner <tglx@linutronix.de>
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Cc: linux-kernel@vger.kernel.org
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Fixes: 660da7c9228f ("x86/mm: Enable CR4.PCIDE on supported systems")
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit c7ad5ad297e644601747d6dbee978bf85e14f7bc)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 0e6a37a43aa876327e7d21881c09977da2d5c270)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/kernel/cpu/common.c | 49 +++++++-------------------------------------
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arch/x86/kernel/setup.c | 5 ++++-
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arch/x86/kernel/smpboot.c | 8 +++++---
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arch/x86/mm/init.c | 34 ++++++++++++++++++++++++++++++
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4 files changed, 50 insertions(+), 46 deletions(-)
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 0b80ed14ff52..4be7b209a3d6 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -169,21 +169,21 @@ static int __init x86_mpx_setup(char *s)
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__setup("nompx", x86_mpx_setup);
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#ifdef CONFIG_X86_64
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-static int __init x86_pcid_setup(char *s)
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+static int __init x86_nopcid_setup(char *s)
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{
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- /* require an exact match without trailing characters */
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- if (strlen(s))
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- return 0;
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+ /* nopcid doesn't accept parameters */
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+ if (s)
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+ return -EINVAL;
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/* do not emit a message if the feature is not present */
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if (!boot_cpu_has(X86_FEATURE_PCID))
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- return 1;
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+ return 0;
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setup_clear_cpu_cap(X86_FEATURE_PCID);
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pr_info("nopcid: PCID feature disabled\n");
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- return 1;
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+ return 0;
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}
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-__setup("nopcid", x86_pcid_setup);
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+early_param("nopcid", x86_nopcid_setup);
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#endif
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static int __init x86_noinvpcid_setup(char *s)
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@@ -329,38 +329,6 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
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}
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}
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-static void setup_pcid(struct cpuinfo_x86 *c)
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-{
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- if (cpu_has(c, X86_FEATURE_PCID)) {
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- if (cpu_has(c, X86_FEATURE_PGE)) {
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- /*
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- * We'd like to use cr4_set_bits_and_update_boot(),
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- * but we can't. CR4.PCIDE is special and can only
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- * be set in long mode, and the early CPU init code
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- * doesn't know this and would try to restore CR4.PCIDE
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- * prior to entering long mode.
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- *
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- * Instead, we rely on the fact that hotplug, resume,
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- * etc all fully restore CR4 before they write anything
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- * that could have nonzero PCID bits to CR3. CR4.PCIDE
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- * has no effect on the page tables themselves, so we
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- * don't need it to be restored early.
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- */
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- cr4_set_bits(X86_CR4_PCIDE);
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- } else {
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- /*
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- * flush_tlb_all(), as currently implemented, won't
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- * work if PCID is on but PGE is not. Since that
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- * combination doesn't exist on real hardware, there's
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- * no reason to try to fully support it, but it's
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- * polite to avoid corrupting data if we're on
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- * an improperly configured VM.
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- */
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- clear_cpu_cap(c, X86_FEATURE_PCID);
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- }
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- }
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-}
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-
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/*
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* Protection Keys are not available in 32-bit mode.
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*/
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@@ -1175,9 +1143,6 @@ static void identify_cpu(struct cpuinfo_x86 *c)
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setup_smep(c);
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setup_smap(c);
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- /* Set up PCID */
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- setup_pcid(c);
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-
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/*
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* The vendor-specific functions might have changed features.
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* Now we do "generic changes."
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diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
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index d7e8b983aa72..f964bfddfefd 100644
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--- a/arch/x86/kernel/setup.c
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+++ b/arch/x86/kernel/setup.c
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@@ -1174,8 +1174,11 @@ void __init setup_arch(char **cmdline_p)
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* with the current CR4 value. This may not be necessary, but
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* auditing all the early-boot CR4 manipulation would be needed to
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* rule it out.
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+ *
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+ * Mask off features that don't work outside long mode (just
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+ * PCIDE for now).
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*/
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- mmu_cr4_features = __read_cr4();
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+ mmu_cr4_features = __read_cr4() & ~X86_CR4_PCIDE;
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memblock_set_current_limit(get_max_mapped());
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diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
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index 893fd8c849e2..d05006f6c31c 100644
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--- a/arch/x86/kernel/smpboot.c
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+++ b/arch/x86/kernel/smpboot.c
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@@ -227,10 +227,12 @@ static int enable_start_cpu0;
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static void notrace start_secondary(void *unused)
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{
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/*
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- * Don't put *anything* before cpu_init(), SMP booting is too
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- * fragile that we want to limit the things done here to the
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- * most necessary things.
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+ * Don't put *anything* except direct CPU state initialization
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+ * before cpu_init(), SMP booting is too fragile that we want to
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+ * limit the things done here to the most necessary things.
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*/
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+ if (boot_cpu_has(X86_FEATURE_PCID))
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+ __write_cr4(__read_cr4() | X86_CR4_PCIDE);
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cpu_init();
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x86_cpuinit.early_percpu_clock_init();
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preempt_disable();
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diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
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index bf3f1065d6ad..df2624b091a7 100644
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--- a/arch/x86/mm/init.c
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+++ b/arch/x86/mm/init.c
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@@ -19,6 +19,7 @@
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#include <asm/microcode.h>
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#include <asm/kaslr.h>
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#include <asm/hypervisor.h>
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+#include <asm/cpufeature.h>
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/*
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* We need to define the tracepoints somewhere, and tlb.c
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@@ -193,6 +194,38 @@ static void __init probe_page_size_mask(void)
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}
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}
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+static void setup_pcid(void)
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+{
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+#ifdef CONFIG_X86_64
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+ if (boot_cpu_has(X86_FEATURE_PCID)) {
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+ if (boot_cpu_has(X86_FEATURE_PGE)) {
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+ /*
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+ * This can't be cr4_set_bits_and_update_boot() --
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+ * the trampoline code can't handle CR4.PCIDE and
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+ * it wouldn't do any good anyway. Despite the name,
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+ * cr4_set_bits_and_update_boot() doesn't actually
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+ * cause the bits in question to remain set all the
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+ * way through the secondary boot asm.
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+ *
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+ * Instead, we brute-force it and set CR4.PCIDE
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+ * manually in start_secondary().
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+ */
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+ cr4_set_bits(X86_CR4_PCIDE);
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+ } else {
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+ /*
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+ * flush_tlb_all(), as currently implemented, won't
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+ * work if PCID is on but PGE is not. Since that
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+ * combination doesn't exist on real hardware, there's
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+ * no reason to try to fully support it, but it's
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+ * polite to avoid corrupting data if we're on
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+ * an improperly configured VM.
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+ */
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+ setup_clear_cpu_cap(X86_FEATURE_PCID);
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+ }
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+ }
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+#endif
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+}
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+
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#ifdef CONFIG_X86_32
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#define NR_RANGE_MR 3
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#else /* CONFIG_X86_64 */
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@@ -592,6 +625,7 @@ void __init init_mem_mapping(void)
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unsigned long end;
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probe_page_size_mask();
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+ setup_pcid();
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#ifdef CONFIG_X86_64
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end = max_pfn << PAGE_SHIFT;
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--
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2.14.2
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