121 lines
4.0 KiB
Diff
121 lines
4.0 KiB
Diff
From bbdde34293757490c18c57d8bd9f92e567bbdbcd Mon Sep 17 00:00:00 2001
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From: Andy Lutomirski <luto@kernel.org>
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Date: Thu, 29 Jun 2017 08:53:21 -0700
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Subject: [PATCH 016/231] x86/mm: Enable CR4.PCIDE on supported systems
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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We can use PCID if the CPU has PCID and PGE and we're not on Xen.
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By itself, this has no effect. A followup patch will start using PCID.
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Signed-off-by: Andy Lutomirski <luto@kernel.org>
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Reviewed-by: Nadav Amit <nadav.amit@gmail.com>
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Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andrew Morton <akpm@linux-foundation.org>
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Cc: Arjan van de Ven <arjan@linux.intel.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Dave Hansen <dave.hansen@intel.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Mel Gorman <mgorman@suse.de>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Rik van Riel <riel@redhat.com>
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Cc: linux-mm@kvack.org
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Link: http://lkml.kernel.org/r/6327ecd907b32f79d5aa0d466f04503bbec5df88.1498751203.git.luto@kernel.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 660da7c9228f685b2ebe664f9fd69aaddcc420b5)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 7d6bbe5528395f18de50bd2532843546c849883d)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/tlbflush.h | 8 ++++++++
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arch/x86/kernel/cpu/common.c | 22 ++++++++++++++++++++++
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arch/x86/xen/enlighten_pv.c | 6 ++++++
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3 files changed, 36 insertions(+)
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index 50ea3482e1d1..2b3d68093235 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -207,6 +207,14 @@ static inline void __flush_tlb_all(void)
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__flush_tlb_global();
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else
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__flush_tlb();
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+
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+ /*
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+ * Note: if we somehow had PCID but not PGE, then this wouldn't work --
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+ * we'd end up flushing kernel translations for the current ASID but
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+ * we might fail to flush kernel translations for other cached ASIDs.
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+ *
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+ * To avoid this issue, we force PCID off if PGE is off.
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+ */
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}
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static inline void __flush_tlb_one(unsigned long addr)
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diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
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index 904485e7b230..b95cd94ca97b 100644
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--- a/arch/x86/kernel/cpu/common.c
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+++ b/arch/x86/kernel/cpu/common.c
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@@ -329,6 +329,25 @@ static __always_inline void setup_smap(struct cpuinfo_x86 *c)
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}
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}
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+static void setup_pcid(struct cpuinfo_x86 *c)
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+{
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+ if (cpu_has(c, X86_FEATURE_PCID)) {
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+ if (cpu_has(c, X86_FEATURE_PGE)) {
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+ cr4_set_bits(X86_CR4_PCIDE);
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+ } else {
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+ /*
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+ * flush_tlb_all(), as currently implemented, won't
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+ * work if PCID is on but PGE is not. Since that
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+ * combination doesn't exist on real hardware, there's
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+ * no reason to try to fully support it, but it's
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+ * polite to avoid corrupting data if we're on
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+ * an improperly configured VM.
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+ */
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+ clear_cpu_cap(c, X86_FEATURE_PCID);
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+ }
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+ }
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+}
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+
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/*
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* Protection Keys are not available in 32-bit mode.
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*/
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@@ -1143,6 +1162,9 @@ static void identify_cpu(struct cpuinfo_x86 *c)
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setup_smep(c);
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setup_smap(c);
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+ /* Set up PCID */
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+ setup_pcid(c);
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+
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/*
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* The vendor-specific functions might have changed features.
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* Now we do "generic changes."
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diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
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index 811e4ddb3f37..290bc5ac9852 100644
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--- a/arch/x86/xen/enlighten_pv.c
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+++ b/arch/x86/xen/enlighten_pv.c
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@@ -264,6 +264,12 @@ static void __init xen_init_capabilities(void)
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setup_clear_cpu_cap(X86_FEATURE_ACC);
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setup_clear_cpu_cap(X86_FEATURE_X2APIC);
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+ /*
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+ * Xen PV would need some work to support PCID: CR3 handling as well
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+ * as xen_flush_tlb_others() would need updating.
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+ */
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+ setup_clear_cpu_cap(X86_FEATURE_PCID);
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+
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if (!xen_initial_domain())
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setup_clear_cpu_cap(X86_FEATURE_ACPI);
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--
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2.14.2
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