73 lines
2.6 KiB
Diff
73 lines
2.6 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: "Borislav Petkov (AMD)" <bp@alien8.de>
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Date: Sat, 7 Oct 2023 12:57:02 +0200
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Subject: [PATCH] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Fix erratum #1485 on Zen4 parts where running with STIBP disabled can
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cause an #UD exception. The performance impact of the fix is negligible.
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Reported-by: René Rebe <rene@exactcode.de>
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Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
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Tested-by: René Rebe <rene@exactcode.de>
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Cc: <stable@kernel.org>
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Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
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Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
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---
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arch/x86/include/asm/msr-index.h | 9 +++++++--
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arch/x86/kernel/cpu/amd.c | 8 ++++++++
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2 files changed, 15 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index ebbf80d8b8bd..a79b10e57757 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -630,12 +630,17 @@
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/* AMD Last Branch Record MSRs */
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#define MSR_AMD64_LBR_SELECT 0xc000010e
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-/* Fam 17h MSRs */
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-#define MSR_F17H_IRPERF 0xc00000e9
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+/* Zen4 */
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+#define MSR_ZEN4_BP_CFG 0xc001102e
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+#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
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+/* Zen 2 */
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#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
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#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
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+/* Fam 17h MSRs */
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+#define MSR_F17H_IRPERF 0xc00000e9
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+
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/* Fam 16h MSRs */
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#define MSR_F16H_L2I_PERF_CTL 0xc0010230
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#define MSR_F16H_L2I_PERF_CTR 0xc0010231
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diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
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index 6daf6a8fa0c7..044e3869620c 100644
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -79,6 +79,10 @@ static const int amd_div0[] =
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AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
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AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
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+static const int amd_erratum_1485[] =
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+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
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+ AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
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+
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static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
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{
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int osvw_id = *erratum++;
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@@ -1124,6 +1128,10 @@ static void init_amd(struct cpuinfo_x86 *c)
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pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
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setup_force_cpu_bug(X86_BUG_DIV0);
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}
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+
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+ if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
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+ cpu_has_amd_erratum(c, amd_erratum_1485))
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+ msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
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}
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#ifdef CONFIG_X86_32
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