180 lines
6.7 KiB
Diff
180 lines
6.7 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Dave Hansen <dave.hansen@linux.intel.com>
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Date: Mon, 4 Dec 2017 15:07:54 +0100
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Subject: [PATCH] x86/mm: Move the CR3 construction functions to tlbflush.h
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5754
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For flushing the TLB, the ASID which has been programmed into the hardware
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must be known. That differs from what is in 'cpu_tlbstate'.
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Add functions to transform the 'cpu_tlbstate' values into to the one
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programmed into the hardware (CR3).
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It's not easy to include mmu_context.h into tlbflush.h, so just move the
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CR3 building over to tlbflush.h.
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Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
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Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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Cc: Andy Lutomirski <luto@kernel.org>
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Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
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Cc: Borislav Petkov <bp@alien8.de>
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Cc: Brian Gerst <brgerst@gmail.com>
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Cc: David Laight <David.Laight@aculab.com>
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Cc: Denys Vlasenko <dvlasenk@redhat.com>
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Cc: Eduardo Valentin <eduval@amazon.com>
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Cc: Greg KH <gregkh@linuxfoundation.org>
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Cc: H. Peter Anvin <hpa@zytor.com>
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Cc: Josh Poimboeuf <jpoimboe@redhat.com>
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Cc: Juergen Gross <jgross@suse.com>
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Cc: Linus Torvalds <torvalds@linux-foundation.org>
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Cc: Peter Zijlstra <peterz@infradead.org>
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Cc: Will Deacon <will.deacon@arm.com>
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Cc: aliguori@amazon.com
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Cc: daniel.gruss@iaik.tugraz.at
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Cc: hughd@google.com
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Cc: keescook@google.com
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Cc: linux-mm@kvack.org
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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(cherry picked from commit 50fb83a62cf472dc53ba23bd3f7bd6c1b2b3b53e)
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit f741923acf51c1061c11b45a168f8864d37dc5cd)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/mmu_context.h | 29 +----------------------------
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arch/x86/include/asm/tlbflush.h | 26 ++++++++++++++++++++++++++
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arch/x86/mm/tlb.c | 8 ++++----
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3 files changed, 31 insertions(+), 32 deletions(-)
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diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
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index 47ec51a821e8..89a01ad7e370 100644
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--- a/arch/x86/include/asm/mmu_context.h
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+++ b/arch/x86/include/asm/mmu_context.h
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@@ -289,33 +289,6 @@ static inline bool arch_vma_access_permitted(struct vm_area_struct *vma,
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return __pkru_allows_pkey(vma_pkey(vma), write);
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}
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-/*
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- * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
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- * bits. This serves two purposes. It prevents a nasty situation in
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- * which PCID-unaware code saves CR3, loads some other value (with PCID
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- * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
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- * the saved ASID was nonzero. It also means that any bugs involving
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- * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
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- * deterministically.
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- */
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-
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-static inline unsigned long build_cr3(struct mm_struct *mm, u16 asid)
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-{
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- if (static_cpu_has(X86_FEATURE_PCID)) {
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- VM_WARN_ON_ONCE(asid > 4094);
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- return __sme_pa(mm->pgd) | (asid + 1);
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- } else {
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- VM_WARN_ON_ONCE(asid != 0);
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- return __sme_pa(mm->pgd);
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- }
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-}
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-
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-static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid)
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-{
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- VM_WARN_ON_ONCE(asid > 4094);
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- return __sme_pa(mm->pgd) | (asid + 1) | CR3_NOFLUSH;
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-}
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-
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/*
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* This can be used from process context to figure out what the value of
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* CR3 is without needing to do a (slow) __read_cr3().
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@@ -325,7 +298,7 @@ static inline unsigned long build_cr3_noflush(struct mm_struct *mm, u16 asid)
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*/
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static inline unsigned long __get_current_cr3_fast(void)
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{
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- unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm),
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+ unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
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this_cpu_read(cpu_tlbstate.loaded_mm_asid));
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/* For now, be very restrictive about when this can be called. */
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diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
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index ed5d483c4a1b..3a421b164868 100644
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -68,6 +68,32 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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return atomic64_inc_return(&mm->context.tlb_gen);
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}
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+/*
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+ * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID bits.
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+ * This serves two purposes. It prevents a nasty situation in which
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+ * PCID-unaware code saves CR3, loads some other value (with PCID == 0),
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+ * and then restores CR3, thus corrupting the TLB for ASID 0 if the saved
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+ * ASID was nonzero. It also means that any bugs involving loading a
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+ * PCID-enabled CR3 with CR4.PCIDE off will trigger deterministically.
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+ */
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+struct pgd_t;
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+static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
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+{
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+ if (static_cpu_has(X86_FEATURE_PCID)) {
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+ VM_WARN_ON_ONCE(asid > 4094);
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+ return __sme_pa(pgd) | (asid + 1);
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+ } else {
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+ VM_WARN_ON_ONCE(asid != 0);
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+ return __sme_pa(pgd);
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+ }
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+}
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+
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+static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
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+{
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+ VM_WARN_ON_ONCE(asid > 4094);
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+ return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
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+}
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+
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
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index 5b4342c5039c..87d4f961bcb4 100644
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--- a/arch/x86/mm/tlb.c
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+++ b/arch/x86/mm/tlb.c
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@@ -126,7 +126,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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* does something like write_cr3(read_cr3_pa()).
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*/
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#ifdef CONFIG_DEBUG_VM
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- if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev, prev_asid))) {
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+ if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
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/*
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* If we were to BUG here, we'd be very likely to kill
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* the system so hard that we don't see the call trace.
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@@ -193,7 +193,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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if (need_flush) {
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
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this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
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- write_cr3(build_cr3(next, new_asid));
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+ write_cr3(build_cr3(next->pgd, new_asid));
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/*
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* NB: This gets called via leave_mm() in the idle path
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@@ -206,7 +206,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
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} else {
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/* The new ASID is already up to date. */
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- write_cr3(build_cr3_noflush(next, new_asid));
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+ write_cr3(build_cr3_noflush(next->pgd, new_asid));
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/* See above wrt _rcuidle. */
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trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
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@@ -283,7 +283,7 @@ void initialize_tlbstate_and_flush(void)
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!(cr4_read_shadow() & X86_CR4_PCIDE));
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/* Force ASID 0 and force a TLB flush. */
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- write_cr3(build_cr3(mm, 0));
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+ write_cr3(build_cr3(mm->pgd, 0));
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/* Reinitialize tlbstate. */
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this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
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--
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2.14.2
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