73 lines
2.6 KiB
Diff
73 lines
2.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
|
From: "Borislav Petkov (AMD)" <bp@alien8.de>
|
|
Date: Sat, 7 Oct 2023 12:57:02 +0200
|
|
Subject: [PATCH] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Fix erratum #1485 on Zen4 parts where running with STIBP disabled can
|
|
cause an #UD exception. The performance impact of the fix is negligible.
|
|
|
|
Reported-by: René Rebe <rene@exactcode.de>
|
|
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
|
|
Tested-by: René Rebe <rene@exactcode.de>
|
|
Cc: <stable@kernel.org>
|
|
Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
|
|
Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
|
|
---
|
|
arch/x86/include/asm/msr-index.h | 9 +++++++--
|
|
arch/x86/kernel/cpu/amd.c | 8 ++++++++
|
|
2 files changed, 15 insertions(+), 2 deletions(-)
|
|
|
|
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
|
|
index ebbf80d8b8bd..a79b10e57757 100644
|
|
--- a/arch/x86/include/asm/msr-index.h
|
|
+++ b/arch/x86/include/asm/msr-index.h
|
|
@@ -630,12 +630,17 @@
|
|
/* AMD Last Branch Record MSRs */
|
|
#define MSR_AMD64_LBR_SELECT 0xc000010e
|
|
|
|
-/* Fam 17h MSRs */
|
|
-#define MSR_F17H_IRPERF 0xc00000e9
|
|
+/* Zen4 */
|
|
+#define MSR_ZEN4_BP_CFG 0xc001102e
|
|
+#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
|
|
|
|
+/* Zen 2 */
|
|
#define MSR_ZEN2_SPECTRAL_CHICKEN 0xc00110e3
|
|
#define MSR_ZEN2_SPECTRAL_CHICKEN_BIT BIT_ULL(1)
|
|
|
|
+/* Fam 17h MSRs */
|
|
+#define MSR_F17H_IRPERF 0xc00000e9
|
|
+
|
|
/* Fam 16h MSRs */
|
|
#define MSR_F16H_L2I_PERF_CTL 0xc0010230
|
|
#define MSR_F16H_L2I_PERF_CTR 0xc0010231
|
|
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
|
|
index 6daf6a8fa0c7..044e3869620c 100644
|
|
--- a/arch/x86/kernel/cpu/amd.c
|
|
+++ b/arch/x86/kernel/cpu/amd.c
|
|
@@ -79,6 +79,10 @@ static const int amd_div0[] =
|
|
AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
|
|
AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
|
|
|
|
+static const int amd_erratum_1485[] =
|
|
+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
|
|
+ AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
|
|
+
|
|
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
|
|
{
|
|
int osvw_id = *erratum++;
|
|
@@ -1124,6 +1128,10 @@ static void init_amd(struct cpuinfo_x86 *c)
|
|
pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
|
|
setup_force_cpu_bug(X86_BUG_DIV0);
|
|
}
|
|
+
|
|
+ if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
|
|
+ cpu_has_amd_erratum(c, amd_erratum_1485))
|
|
+ msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_32
|