118 lines
3.6 KiB
Diff
118 lines
3.6 KiB
Diff
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Tim Chen <tim.c.chen@linux.intel.com>
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Date: Mon, 6 Nov 2017 18:19:14 -0800
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Subject: [PATCH] x86/idle: Disable IBRS entering idle and enable it on wakeup
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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Clear IBRS on idle entry and set it on idle exit into kernel on mwait.
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Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit 5521b04afda1d683c1ebad6c25c2529a88e6f061)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/mwait.h | 8 ++++++++
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arch/x86/kernel/process.c | 12 ++++++++++--
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arch/x86/lib/delay.c | 10 ++++++++++
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3 files changed, 28 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h
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index bda3c27f0da0..f15120ada161 100644
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--- a/arch/x86/include/asm/mwait.h
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+++ b/arch/x86/include/asm/mwait.h
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@@ -5,6 +5,8 @@
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#include <linux/sched/idle.h>
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#include <asm/cpufeature.h>
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+#include <asm/spec_ctrl.h>
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+#include <asm/microcode.h>
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#define MWAIT_SUBSTATE_MASK 0xf
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#define MWAIT_CSTATE_MASK 0xf
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@@ -105,9 +107,15 @@ static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx)
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mb();
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}
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
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+
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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if (!need_resched())
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__mwait(eax, ecx);
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+
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
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}
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current_clr_polling();
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}
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diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
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index 07e6218ad7d9..3adb3806a284 100644
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--- a/arch/x86/kernel/process.c
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+++ b/arch/x86/kernel/process.c
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@@ -447,11 +447,19 @@ static __cpuidle void mwait_idle(void)
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mb(); /* quirk */
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}
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
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+
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__monitor((void *)¤t_thread_info()->flags, 0, 0);
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- if (!need_resched())
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+ if (!need_resched()) {
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__sti_mwait(0, 0);
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- else
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
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+ } else {
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
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local_irq_enable();
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+ }
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trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
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} else {
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local_irq_enable();
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diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
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index cf2ac227c2ac..b088463973e4 100644
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--- a/arch/x86/lib/delay.c
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+++ b/arch/x86/lib/delay.c
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@@ -26,6 +26,8 @@
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# include <asm/smp.h>
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#endif
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+#define IBRS_DISABLE_THRESHOLD 1000
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+
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/* simple loop based delay: */
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static void delay_loop(unsigned long loops)
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{
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@@ -105,6 +107,10 @@ static void delay_mwaitx(unsigned long __loops)
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for (;;) {
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delay = min_t(u64, MWAITX_MAX_LOOPS, loops);
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
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+ (delay > IBRS_DISABLE_THRESHOLD))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, 0);
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+
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/*
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* Use cpu_tss_rw as a cacheline-aligned, seldomly
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* accessed per-cpu variable as the monitor target.
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@@ -118,6 +124,10 @@ static void delay_mwaitx(unsigned long __loops)
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*/
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__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
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+ if (boot_cpu_has(X86_FEATURE_SPEC_CTRL) &&
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+ (delay > IBRS_DISABLE_THRESHOLD))
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+ native_wrmsrl(MSR_IA32_SPEC_CTRL, FEATURE_ENABLE_IBRS);
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+
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end = rdtsc_ordered();
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if (loops <= end - start)
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--
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2.14.2
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