From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Tim Chen <tim.c.chen@linux.intel.com>
Date: Fri, 15 Sep 2017 18:04:53 -0700
Subject: [PATCH] x86/enter: MACROS to set/clear IBRS and set IBPB
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CVE-2017-5753
CVE-2017-5715

Setup macros to control IBRS and IBPB

Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
Signed-off-by: Andy Whitcroft <apw@canonical.com>
Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
(cherry picked from commit 171d754fe3b783d361555cf2569e68a7b0e0d54a)
Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
---
 arch/x86/include/asm/spec_ctrl.h | 52 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 arch/x86/include/asm/spec_ctrl.h

diff --git a/arch/x86/include/asm/spec_ctrl.h b/arch/x86/include/asm/spec_ctrl.h
new file mode 100644
index 000000000000..7f8bb09b6acb
--- /dev/null
+++ b/arch/x86/include/asm/spec_ctrl.h
@@ -0,0 +1,52 @@
+#ifndef _ASM_X86_SPEC_CTRL_H
+#define _ASM_X86_SPEC_CTRL_H
+
+#include <linux/stringify.h>
+#include <asm/msr-index.h>
+#include <asm/cpufeatures.h>
+#include <asm/alternative-asm.h>
+
+#ifdef __ASSEMBLY__
+
+#define __ASM_ENABLE_IBRS			\
+	pushq %rax;				\
+	pushq %rcx;				\
+	pushq %rdx;				\
+	movl $MSR_IA32_SPEC_CTRL, %ecx;		\
+	movl $0, %edx;				\
+	movl $FEATURE_ENABLE_IBRS, %eax;	\
+	wrmsr;					\
+	popq %rdx;				\
+	popq %rcx;				\
+	popq %rax
+#define __ASM_ENABLE_IBRS_CLOBBER		\
+	movl $MSR_IA32_SPEC_CTRL, %ecx;		\
+	movl $0, %edx;				\
+	movl $FEATURE_ENABLE_IBRS, %eax;	\
+	wrmsr;
+#define __ASM_DISABLE_IBRS			\
+	pushq %rax;				\
+	pushq %rcx;				\
+	pushq %rdx;				\
+	movl $MSR_IA32_SPEC_CTRL, %ecx;		\
+	movl $0, %edx;				\
+	movl $0, %eax;				\
+	wrmsr;					\
+	popq %rdx;				\
+	popq %rcx;				\
+	popq %rax
+
+.macro ENABLE_IBRS
+ALTERNATIVE "", __stringify(__ASM_ENABLE_IBRS), X86_FEATURE_SPEC_CTRL
+.endm
+
+.macro ENABLE_IBRS_CLOBBER
+ALTERNATIVE "", __stringify(__ASM_ENABLE_IBRS_CLOBBER), X86_FEATURE_SPEC_CTRL
+.endm
+
+.macro DISABLE_IBRS
+ALTERNATIVE "", __stringify(__ASM_DISABLE_IBRS), X86_FEATURE_SPEC_CTRL
+.endm
+
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_X86_SPEC_CTRL_H */
-- 
2.14.2