cherry-pick fix for RCU stall issue after VM live migration
caused by a lapic timer interrupt getting lost. Already queued for 6.5.13: https://lore.kernel.org/stable/20231124172031.920738810@linuxfoundation.org/ Reported in the community forum: https://forum.proxmox.com/threads/136992/ Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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Fiona Ebner
Thomas Lamprecht
parent
f7fedc604d
commit
cc99d7fd2f
@ -0,0 +1,126 @@
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Date: Fri, 24 Nov 2023 17:48:01 +0000
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Subject: [PATCH] KVM: x86: Fix lapic timer interrupt lost after loading a
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snapshot.
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commit 9cfec6d097c607e36199cf0cfbb8cf5acbd8e9b2 upstream.
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When running android emulator (which is based on QEMU 2.12) on
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certain Intel hosts with kernel version 6.3-rc1 or above, guest
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will freeze after loading a snapshot. This is almost 100%
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reproducible. By default, the android emulator will use snapshot
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to speed up the next launching of the same android guest. So
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this breaks the android emulator badly.
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I tested QEMU 8.0.4 from Debian 12 with an Ubuntu 22.04 guest by
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running command "loadvm" after "savevm". The same issue is
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observed. At the same time, none of our AMD platforms is impacted.
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More experiments show that loading the KVM module with
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"enable_apicv=false" can workaround it.
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The issue started to show up after commit 8e6ed96cdd50 ("KVM: x86:
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fire timer when it is migrated and expired, and in oneshot mode").
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However, as is pointed out by Sean Christopherson, it is introduced
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by commit 967235d32032 ("KVM: vmx: clear pending interrupts on
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KVM_SET_LAPIC"). commit 8e6ed96cdd50 ("KVM: x86: fire timer when
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it is migrated and expired, and in oneshot mode") just makes it
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easier to hit the issue.
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Having both commits, the oneshot lapic timer gets fired immediately
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inside the KVM_SET_LAPIC call when loading the snapshot. On Intel
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platforms with APIC virtualization and posted interrupt processing,
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this eventually leads to setting the corresponding PIR bit. However,
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the whole PIR bits get cleared later in the same KVM_SET_LAPIC call
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by apicv_post_state_restore. This leads to timer interrupt lost.
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The fix is to move vmx_apicv_post_state_restore to the beginning of
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the KVM_SET_LAPIC call and rename to vmx_apicv_pre_state_restore.
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What vmx_apicv_post_state_restore does is actually clearing any
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former apicv state and this behavior is more suitable to carry out
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in the beginning.
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Fixes: 967235d32032 ("KVM: vmx: clear pending interrupts on KVM_SET_LAPIC")
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Cc: stable@vger.kernel.org
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Suggested-by: Sean Christopherson <seanjc@google.com>
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Signed-off-by: Haitao Shan <hshan@google.com>
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Link: https://lore.kernel.org/r/20230913000215.478387-1-hshan@google.com
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Signed-off-by: Sean Christopherson <seanjc@google.com>
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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(picked from https://lore.kernel.org/stable/20231124172031.920738810@linuxfoundation.org/)
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Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
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---
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arch/x86/include/asm/kvm-x86-ops.h | 1 +
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arch/x86/include/asm/kvm_host.h | 1 +
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arch/x86/kvm/lapic.c | 4 ++++
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arch/x86/kvm/vmx/vmx.c | 4 ++--
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4 files changed, 8 insertions(+), 2 deletions(-)
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diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-x86-ops.h
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index e3054e3e46d52..9b419f0de713c 100644
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--- a/arch/x86/include/asm/kvm-x86-ops.h
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+++ b/arch/x86/include/asm/kvm-x86-ops.h
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@@ -108,6 +108,7 @@ KVM_X86_OP_OPTIONAL(vcpu_blocking)
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KVM_X86_OP_OPTIONAL(vcpu_unblocking)
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KVM_X86_OP_OPTIONAL(pi_update_irte)
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KVM_X86_OP_OPTIONAL(pi_start_assignment)
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+KVM_X86_OP_OPTIONAL(apicv_pre_state_restore)
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KVM_X86_OP_OPTIONAL(apicv_post_state_restore)
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KVM_X86_OP_OPTIONAL_RET0(dy_apicv_has_pending_interrupt)
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KVM_X86_OP_OPTIONAL(set_hv_timer)
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diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
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index f72b30d2238a6..9bdbb1cc03d38 100644
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--- a/arch/x86/include/asm/kvm_host.h
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+++ b/arch/x86/include/asm/kvm_host.h
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@@ -1690,6 +1690,7 @@ struct kvm_x86_ops {
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int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq,
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uint32_t guest_irq, bool set);
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void (*pi_start_assignment)(struct kvm *kvm);
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+ void (*apicv_pre_state_restore)(struct kvm_vcpu *vcpu);
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void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
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bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
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diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
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index e74e223f46aa3..a3d488608b85d 100644
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--- a/arch/x86/kvm/lapic.c
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+++ b/arch/x86/kvm/lapic.c
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@@ -2649,6 +2649,8 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
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u64 msr_val;
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int i;
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+ static_call_cond(kvm_x86_apicv_pre_state_restore)(vcpu);
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+
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if (!init_event) {
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msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
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if (kvm_vcpu_is_reset_bsp(vcpu))
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@@ -2960,6 +2962,8 @@ int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
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struct kvm_lapic *apic = vcpu->arch.apic;
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int r;
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+ static_call_cond(kvm_x86_apicv_pre_state_restore)(vcpu);
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+
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kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
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/* set SPIV separately to get count of SW disabled APICs right */
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apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
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diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
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index bc6f0fea48b43..52af279f793db 100644
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--- a/arch/x86/kvm/vmx/vmx.c
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+++ b/arch/x86/kvm/vmx/vmx.c
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@@ -6909,7 +6909,7 @@ static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
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vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
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}
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-static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
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+static void vmx_apicv_pre_state_restore(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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@@ -8275,7 +8275,7 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = {
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.set_apic_access_page_addr = vmx_set_apic_access_page_addr,
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.refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
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.load_eoi_exitmap = vmx_load_eoi_exitmap,
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- .apicv_post_state_restore = vmx_apicv_post_state_restore,
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+ .apicv_pre_state_restore = vmx_apicv_pre_state_restore,
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.required_apicv_inhibits = VMX_REQUIRED_APICV_INHIBITS,
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.hwapic_irr_update = vmx_hwapic_irr_update,
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.hwapic_isr_update = vmx_hwapic_isr_update,
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