From 9ba0dde971e6153a12f94e9c7a7337355ab3d0ed Mon Sep 17 00:00:00 2001 From: Thomas Lamprecht Date: Tue, 19 Sep 2023 09:27:09 +0200 Subject: [PATCH] cherry-pick fix for setting X86_FEATURE_OSXSAVE feature Avoids regressions where some code falsely think they cannot use some CPU features like AVX1, e.g., ZFS. Signed-off-by: Thomas Lamprecht --- ...FEATURE_OSXSAVE-feature-after-enabli.patch | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 patches/kernel/0016-x86-fpu-Set-X86_FEATURE_OSXSAVE-feature-after-enabli.patch diff --git a/patches/kernel/0016-x86-fpu-Set-X86_FEATURE_OSXSAVE-feature-after-enabli.patch b/patches/kernel/0016-x86-fpu-Set-X86_FEATURE_OSXSAVE-feature-after-enabli.patch new file mode 100644 index 0000000..c82e202 --- /dev/null +++ b/patches/kernel/0016-x86-fpu-Set-X86_FEATURE_OSXSAVE-feature-after-enabli.patch @@ -0,0 +1,61 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Feng Tang +Date: Wed, 23 Aug 2023 14:57:47 +0800 +Subject: [PATCH] x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling + OSXSAVE in CR4 + +0-Day found a 34.6% regression in stress-ng's 'af-alg' test case, and +bisected it to commit b81fac906a8f ("x86/fpu: Move FPU initialization into +arch_cpu_finalize_init()"), which optimizes the FPU init order, and moves +the CR4_OSXSAVE enabling into a later place: + + arch_cpu_finalize_init + identify_boot_cpu + identify_cpu + generic_identify + get_cpu_cap --> setup cpu capability + ... + fpu__init_cpu + fpu__init_cpu_xstate + cr4_set_bits(X86_CR4_OSXSAVE); + +As the FPU is not yet initialized the CPU capability setup fails to set +X86_FEATURE_OSXSAVE. Many security module like 'camellia_aesni_avx_x86_64' +depend on this feature and therefore fail to load, causing the regression. + +Cure this by setting X86_FEATURE_OSXSAVE feature right after OSXSAVE +enabling. + +[ tglx: Moved it into the actual BSP FPU initialization code and added a comment ] + +Fixes: b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()") +Reported-by: kernel test robot +Signed-off-by: Feng Tang +Signed-off-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/lkml/202307192135.203ac24e-oliver.sang@intel.com +Link: https://lore.kernel.org/lkml/20230823065747.92257-1-feng.tang@intel.com +(cherry picked from commit 2c66ca3949dc701da7f4c9407f2140ae425683a5) +Signed-off-by: Thomas Lamprecht +--- + arch/x86/kernel/fpu/xstate.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c +index 0bab497c9436..1afbc4866b10 100644 +--- a/arch/x86/kernel/fpu/xstate.c ++++ b/arch/x86/kernel/fpu/xstate.c +@@ -882,6 +882,13 @@ void __init fpu__init_system_xstate(unsigned int legacy_size) + goto out_disable; + } + ++ /* ++ * CPU capabilities initialization runs before FPU init. So ++ * X86_FEATURE_OSXSAVE is not set. Now that XSAVE is completely ++ * functional, set the feature bit so depending code works. ++ */ ++ setup_force_cpu_cap(X86_FEATURE_OSXSAVE); ++ + print_xstate_offset_size(); + pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", + fpu_kernel_cfg.max_features,