update Spectre KVM PoC fix for AMD
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parent
04f3b8beca
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@ -1,4 +1,4 @@
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From c59a61438e9a8f24a50171ac9d3b98e8f3719d07 Mon Sep 17 00:00:00 2001
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From 711a55c9d58955a2bfca89cd25935ca607e49bc0 Mon Sep 17 00:00:00 2001
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From: Jim Mattson <jmattson@google.com>
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From: Jim Mattson <jmattson@google.com>
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Date: Wed, 3 Jan 2018 14:31:38 -0800
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Date: Wed, 3 Jan 2018 14:31:38 -0800
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Subject: [PATCH 232/241] kvm: vmx: Scrub hardware GPRs at VM-exit
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Subject: [PATCH 232/241] kvm: vmx: Scrub hardware GPRs at VM-exit
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@ -18,11 +18,44 @@ Signed-off-by: Jim Mattson <jmattson@google.com>
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Reviewed-by: Eric Northup <digitaleric@google.com>
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Reviewed-by: Eric Northup <digitaleric@google.com>
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Reviewed-by: Benjamin Serebrin <serebrin@google.com>
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Reviewed-by: Benjamin Serebrin <serebrin@google.com>
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Reviewed-by: Andrew Honig <ahonig@google.com>
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Reviewed-by: Andrew Honig <ahonig@google.com>
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[Paolo: Add AMD bits, Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>]
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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---
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arch/x86/kvm/svm.c | 19 +++++++++++++++++++
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arch/x86/kvm/vmx.c | 14 +++++++++++++-
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arch/x86/kvm/vmx.c | 14 +++++++++++++-
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1 file changed, 13 insertions(+), 1 deletion(-)
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2 files changed, 32 insertions(+), 1 deletion(-)
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diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
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index af09baa3d736..92cd94d51e1f 100644
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--- a/arch/x86/kvm/svm.c
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+++ b/arch/x86/kvm/svm.c
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@@ -4924,6 +4924,25 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu)
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"mov %%r13, %c[r13](%[svm]) \n\t"
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"mov %%r14, %c[r14](%[svm]) \n\t"
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"mov %%r15, %c[r15](%[svm]) \n\t"
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+#endif
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+ /*
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+ * Clear host registers marked as clobbered to prevent
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+ * speculative use.
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+ */
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+ "xor %%" _ASM_BX ", %%" _ASM_BX " \n\t"
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+ "xor %%" _ASM_CX ", %%" _ASM_CX " \n\t"
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+ "xor %%" _ASM_DX ", %%" _ASM_DX " \n\t"
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+ "xor %%" _ASM_SI ", %%" _ASM_SI " \n\t"
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+ "xor %%" _ASM_DI ", %%" _ASM_DI " \n\t"
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+#ifdef CONFIG_X86_64
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+ "xor %%r8, %%r8 \n\t"
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+ "xor %%r9, %%r9 \n\t"
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+ "xor %%r10, %%r10 \n\t"
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+ "xor %%r11, %%r11 \n\t"
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+ "xor %%r12, %%r12 \n\t"
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+ "xor %%r13, %%r13 \n\t"
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+ "xor %%r14, %%r14 \n\t"
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+ "xor %%r15, %%r15 \n\t"
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#endif
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"pop %%" _ASM_BP
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:
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diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
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diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
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index d61986a36575..9b4256fd589a 100644
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index d61986a36575..9b4256fd589a 100644
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--- a/arch/x86/kvm/vmx.c
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--- a/arch/x86/kvm/vmx.c
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@ -1,4 +1,4 @@
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From a87e8a4126593de7ea94dcc2695f6cd879656c26 Mon Sep 17 00:00:00 2001
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From 4047df49cf44e46d8a213373a8bd5949fd4ef4a6 Mon Sep 17 00:00:00 2001
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From: Marcelo Henrique Cerri <marcelo.cerri@canonical.com>
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From: Marcelo Henrique Cerri <marcelo.cerri@canonical.com>
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Date: Sat, 6 Jan 2018 17:50:34 -0200
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Date: Sat, 6 Jan 2018 17:50:34 -0200
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Subject: [PATCH 233/241] objtool: use sh to invoke sync-check.sh in the
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Subject: [PATCH 233/241] objtool: use sh to invoke sync-check.sh in the
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@ -1,4 +1,4 @@
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From 6d702112480b7badb937ca28544c0d792f175aee Mon Sep 17 00:00:00 2001
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From 2b75ea581156c7f6d53cf736167e2d32c7087af5 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Thu, 4 Jan 2018 22:19:04 +0100
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Date: Thu, 4 Jan 2018 22:19:04 +0100
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Subject: [PATCH 234/241] x86/tlb: Drop the _GPL from the cpu_tlbstate export
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Subject: [PATCH 234/241] x86/tlb: Drop the _GPL from the cpu_tlbstate export
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@ -1,4 +1,4 @@
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From c6f5260d936ad762ce457623aac1b261ed6c4714 Mon Sep 17 00:00:00 2001
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From 35f252cc11a7fc0009caf1a088cbb5d47a60ab50 Mon Sep 17 00:00:00 2001
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From: Peter Zijlstra <peterz@infradead.org>
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From: Peter Zijlstra <peterz@infradead.org>
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Date: Thu, 4 Jan 2018 18:07:12 +0100
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Date: Thu, 4 Jan 2018 18:07:12 +0100
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Subject: [PATCH 235/241] x86/events/intel/ds: Use the proper cache flush
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Subject: [PATCH 235/241] x86/events/intel/ds: Use the proper cache flush
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@ -1,4 +1,4 @@
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From 08716ab53e917eec6d51d4e53dfffbb25e0edd8e Mon Sep 17 00:00:00 2001
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From 650929f1bdce50bab031b0886ae91d459edcd18e Mon Sep 17 00:00:00 2001
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From: Andrey Ryabinin <aryabinin@virtuozzo.com>
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From: Andrey Ryabinin <aryabinin@virtuozzo.com>
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Date: Thu, 28 Dec 2017 19:06:20 +0300
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Date: Thu, 28 Dec 2017 19:06:20 +0300
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Subject: [PATCH 236/241] x86/mm: Set MODULES_END to 0xffffffffff000000
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Subject: [PATCH 236/241] x86/mm: Set MODULES_END to 0xffffffffff000000
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@ -1,4 +1,4 @@
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From 596ad95567b9dedff8b9f43b5ae18b1e3463da6b Mon Sep 17 00:00:00 2001
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From 9ec7ffb2871c23d5c0961f0241bd118ca2395edb Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Thu, 4 Jan 2018 13:01:40 +0100
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Date: Thu, 4 Jan 2018 13:01:40 +0100
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Subject: [PATCH 237/241] x86/mm: Map cpu_entry_area at the same place on 4/5
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Subject: [PATCH 237/241] x86/mm: Map cpu_entry_area at the same place on 4/5
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@ -1,4 +1,4 @@
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From 6d7f23c421d2fc74c052c03fb9735effd98ef035 Mon Sep 17 00:00:00 2001
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From 58d3cea9911d75f766b67dfc639405360b6ee6e5 Mon Sep 17 00:00:00 2001
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From: Thomas Gleixner <tglx@linutronix.de>
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From: Thomas Gleixner <tglx@linutronix.de>
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Date: Thu, 4 Jan 2018 12:32:03 +0100
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Date: Thu, 4 Jan 2018 12:32:03 +0100
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Subject: [PATCH 238/241] x86/kaslr: Fix the vaddr_end mess
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Subject: [PATCH 238/241] x86/kaslr: Fix the vaddr_end mess
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@ -1,4 +1,4 @@
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From 732d51fab3401054c84be53feec624c6c992fb3f Mon Sep 17 00:00:00 2001
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From fe5fdc3484283039f5f7477874eeef1a26f2b6be Mon Sep 17 00:00:00 2001
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From: David Woodhouse <dwmw@amazon.co.uk>
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From: David Woodhouse <dwmw@amazon.co.uk>
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Date: Thu, 4 Jan 2018 14:37:05 +0000
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Date: Thu, 4 Jan 2018 14:37:05 +0000
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Subject: [PATCH 239/241] x86/alternatives: Add missing '\n' at end of
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Subject: [PATCH 239/241] x86/alternatives: Add missing '\n' at end of
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@ -1,4 +1,4 @@
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From 5462db3d070845ecc34929b6f25a87efda023aae Mon Sep 17 00:00:00 2001
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From 309461b2f634fc18271468b4396551ddf6a1dba8 Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Tue, 26 Dec 2017 23:43:54 -0600
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Date: Tue, 26 Dec 2017 23:43:54 -0600
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Subject: [PATCH 240/241] x86/cpu, x86/pti: Do not enable PTI on AMD processors
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Subject: [PATCH 240/241] x86/cpu, x86/pti: Do not enable PTI on AMD processors
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@ -1,4 +1,4 @@
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From 8329d47141a78a64e8ae6f4a735aceaafe93e098 Mon Sep 17 00:00:00 2001
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From 674b72ef0eb73751e4f838dc789e4c393d225834 Mon Sep 17 00:00:00 2001
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From: Tom Lendacky <thomas.lendacky@amd.com>
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From: Tom Lendacky <thomas.lendacky@amd.com>
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Date: Thu, 30 Nov 2017 16:46:40 -0600
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Date: Thu, 30 Nov 2017 16:46:40 -0600
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Subject: [PATCH 241/241] x86/microcode/AMD: Add support for fam17h microcode
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Subject: [PATCH 241/241] x86/microcode/AMD: Add support for fam17h microcode
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