78 lines
3.1 KiB
Diff
78 lines
3.1 KiB
Diff
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
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From: Tim Chen <tim.c.chen@linux.intel.com>
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Date: Thu, 24 Aug 2017 09:34:41 -0700
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Subject: [PATCH] x86/feature: Enable the x86 feature to control Speculation
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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CVE-2017-5753
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CVE-2017-5715
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cpuid ax=0x7, return rdx bit 26 to indicate presence of this feature
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IA32_SPEC_CTRL (0x48) and IA32_PRED_CMD (0x49)
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IA32_SPEC_CTRL, bit0 – Indirect Branch Restricted Speculation (IBRS)
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IA32_PRED_CMD, bit0 – Indirect Branch Prediction Barrier (IBPB)
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Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com>
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Signed-off-by: Andy Whitcroft <apw@canonical.com>
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Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
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(cherry picked from commit f1f160a92b70c25d6e6e76788463bbec86a73313)
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Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
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---
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/msr-index.h | 5 +++++
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arch/x86/kernel/cpu/scattered.c | 1 +
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3 files changed, 7 insertions(+)
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diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
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index 3928050b51b0..44be8fd069bf 100644
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -208,6 +208,7 @@
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#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */
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#define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */
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+#define X86_FEATURE_SPEC_CTRL ( 7*32+19) /* Control Speculation Control */
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/* Virtualization flags: Linux defined, word 8 */
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#define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
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diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
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index db88b7f852b4..4e3438a00a50 100644
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -41,6 +41,9 @@
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#define MSR_PPIN_CTL 0x0000004e
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#define MSR_PPIN 0x0000004f
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+#define MSR_IA32_SPEC_CTRL 0x00000048
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+#define MSR_IA32_PRED_CMD 0x00000049
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+
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_PERFCTR1 0x000000c2
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#define MSR_FSB_FREQ 0x000000cd
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@@ -437,6 +440,8 @@
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#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
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#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
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#define FEATURE_CONTROL_LMCE (1<<20)
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+#define FEATURE_ENABLE_IBRS (1<<0)
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+#define FEATURE_SET_IBPB (1<<0)
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#define MSR_IA32_APICBASE 0x0000001b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
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index 23c23508c012..9651ea395812 100644
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--- a/arch/x86/kernel/cpu/scattered.c
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+++ b/arch/x86/kernel/cpu/scattered.c
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@@ -24,6 +24,7 @@ static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_INTEL_PT, CPUID_EBX, 25, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4VNNIW, CPUID_EDX, 2, 0x00000007, 0 },
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{ X86_FEATURE_AVX512_4FMAPS, CPUID_EDX, 3, 0x00000007, 0 },
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+ { X86_FEATURE_SPEC_CTRL, CPUID_EDX, 26, 0x00000007, 0 },
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{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
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--
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2.14.2
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