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mirror_zfs/module/zfs/vdev_raidz_math_ssse3.c
Gvozden Neskovic c9187d867f Fixes and enhancements of SIMD raidz parity 
- Implementation lock replaced with atomic variable

- Trailing whitespace is removed from user specified parameter, to enhance
experience when using commands that add newline, e.g. `echo`

- raidz_test: remove dependency on `getrusage()` and RUSAGE_THREAD, Issue #4813

- silence `cppcheck` in vdev_raidz, partial solution of Issue #1392

- Minor fixes and cleanups

- Enable use of original parity methods in [fastest] configuration.
New opaque original ops structure, representing native methods, is added
to supported raidz methods. Original parity methods are executed if selected
implementation has NULL fn pointer.

Signed-off-by: Gvozden Neskovic <neskovic@gmail.com>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Issue #4813
Issue #1392
2016-07-19 16:43:07 -07:00

2457 lines
118 KiB
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/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* or http://www.opensolaris.org/os/licensing.
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (C) 2016 Gvozden Nešković. All rights reserved.
*/
#include <sys/isa_defs.h>
#if defined(__x86_64) && defined(HAVE_SSSE3)
#include <sys/types.h>
#include <linux/simd_x86.h>
#define __asm __asm__ __volatile__
#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
#define VR0_(REG, ...) "xmm"#REG
#define VR1_(_1, REG, ...) "xmm"#REG
#define VR2_(_1, _2, REG, ...) "xmm"#REG
#define VR3_(_1, _2, _3, REG, ...) "xmm"#REG
#define VR4_(_1, _2, _3, _4, REG, ...) "xmm"#REG
#define VR5_(_1, _2, _3, _4, _5, REG, ...) "xmm"#REG
#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "xmm"#REG
#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "xmm"#REG
#define VR0(r...) VR0_(r)
#define VR1(r...) VR1_(r)
#define VR2(r...) VR2_(r, 1)
#define VR3(r...) VR3_(r, 1, 2)
#define VR4(r...) VR4_(r, 1, 2)
#define VR5(r...) VR5_(r, 1, 2, 3)
#define VR6(r...) VR6_(r, 1, 2, 3, 4)
#define VR7(r...) VR7_(r, 1, 2, 3, 4, 5)
#define R_01(REG1, REG2, ...) REG1, REG2
#define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3
#define R_23(REG...) _R_23(REG, 1, 2, 3)
#define ASM_BUG() ASSERT(0)
const uint8_t gf_clmul_mod_lt[4*256][16];
#define ELEM_SIZE 16
typedef struct v {
uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
} v_t;
#define PREFETCHNTA(ptr, offset) \
{ \
__asm( \
"prefetchnta " #offset "(%[MEM])\n" \
: : [MEM] "r" (ptr)); \
}
#define PREFETCH(ptr, offset) \
{ \
__asm( \
"prefetcht0 " #offset "(%[MEM])\n" \
: : [MEM] "r" (ptr)); \
}
#define XOR_ACC(src, r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
__asm( \
"pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
"pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
"pxor 0x20(%[SRC]), %%" VR2(r) "\n" \
"pxor 0x30(%[SRC]), %%" VR3(r) "\n" \
: : [SRC] "r" (src)); \
break; \
case 2: \
__asm( \
"pxor 0x00(%[SRC]), %%" VR0(r) "\n" \
"pxor 0x10(%[SRC]), %%" VR1(r) "\n" \
: : [SRC] "r" (src)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define XOR(r...) \
{ \
switch (REG_CNT(r)) { \
case 8: \
__asm( \
"pxor %" VR0(r) ", %" VR4(r) "\n" \
"pxor %" VR1(r) ", %" VR5(r) "\n" \
"pxor %" VR2(r) ", %" VR6(r) "\n" \
"pxor %" VR3(r) ", %" VR7(r)); \
break; \
case 4: \
__asm( \
"pxor %" VR0(r) ", %" VR2(r) "\n" \
"pxor %" VR1(r) ", %" VR3(r)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define COPY(r...) \
{ \
switch (REG_CNT(r)) { \
case 8: \
__asm( \
"movdqa %" VR0(r) ", %" VR4(r) "\n" \
"movdqa %" VR1(r) ", %" VR5(r) "\n" \
"movdqa %" VR2(r) ", %" VR6(r) "\n" \
"movdqa %" VR3(r) ", %" VR7(r)); \
break; \
case 4: \
__asm( \
"movdqa %" VR0(r) ", %" VR2(r) "\n" \
"movdqa %" VR1(r) ", %" VR3(r)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define LOAD(src, r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
__asm( \
"movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
"movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
"movdqa 0x20(%[SRC]), %%" VR2(r) "\n" \
"movdqa 0x30(%[SRC]), %%" VR3(r) "\n" \
: : [SRC] "r" (src)); \
break; \
case 2: \
__asm( \
"movdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
"movdqa 0x10(%[SRC]), %%" VR1(r) "\n" \
: : [SRC] "r" (src)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define STORE(dst, r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
__asm( \
"movdqa %%" VR0(r)", 0x00(%[DST])\n" \
"movdqa %%" VR1(r)", 0x10(%[DST])\n" \
"movdqa %%" VR2(r)", 0x20(%[DST])\n" \
"movdqa %%" VR3(r)", 0x30(%[DST])\n" \
: : [DST] "r" (dst)); \
break; \
case 2: \
__asm( \
"movdqa %%" VR0(r)", 0x00(%[DST])\n" \
"movdqa %%" VR1(r)", 0x10(%[DST])\n" \
: : [DST] "r" (dst)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define MUL2_SETUP() \
{ \
__asm( \
"movd %[mask], %%xmm15\n" \
"pshufd $0x0, %%xmm15, %%xmm15\n" \
: : [mask] "r" (0x1d1d1d1d)); \
}
#define _MUL2_x2(r...) \
{ \
switch (REG_CNT(r)) { \
case 2: \
__asm( \
"pxor %xmm14, %xmm14\n" \
"pxor %xmm13, %xmm13\n" \
"pcmpgtb %" VR0(r)", %xmm14\n" \
"pcmpgtb %" VR1(r)", %xmm13\n" \
"pand %xmm15, %xmm14\n" \
"pand %xmm15, %xmm13\n" \
"paddb %" VR0(r)", %" VR0(r) "\n" \
"paddb %" VR1(r)", %" VR1(r) "\n" \
"pxor %xmm14, %" VR0(r) "\n" \
"pxor %xmm13, %" VR1(r)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define MUL2(r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
_MUL2_x2(R_01(r)); \
_MUL2_x2(R_23(r)); \
break; \
case 2: \
_MUL2_x2(r); \
break; \
default: \
ASM_BUG(); \
} \
}
#define MUL4(r...) \
{ \
MUL2(r); \
MUL2(r); \
}
#define _0f "xmm15"
#define _a_save "xmm14"
#define _b_save "xmm13"
#define _lt_mod_a "xmm12"
#define _lt_clmul_a "xmm11"
#define _lt_mod_b "xmm10"
#define _lt_clmul_b "xmm15"
#define _MULx2(c, r...) \
{ \
switch (REG_CNT(r)) { \
case 2: \
__asm( \
/* lts for upper part */ \
"movd %[mask], %%" _0f "\n" \
"pshufd $0x0, %%" _0f ", %%" _0f "\n" \
"movdqa 0x00(%[lt]), %%" _lt_mod_a "\n" \
"movdqa 0x10(%[lt]), %%" _lt_clmul_a "\n" \
/* upper part */ \
"movdqa %%" VR0(r) ", %%" _a_save "\n" \
"movdqa %%" VR1(r) ", %%" _b_save "\n" \
"psraw $0x4, %%" VR0(r) "\n" \
"psraw $0x4, %%" VR1(r) "\n" \
"pand %%" _0f ", %%" _a_save "\n" \
"pand %%" _0f ", %%" _b_save "\n" \
"pand %%" _0f ", %%" VR0(r) "\n" \
"pand %%" _0f ", %%" VR1(r) "\n" \
\
"movdqa %%" _lt_mod_a ", %%" _lt_mod_b "\n" \
"movdqa %%" _lt_clmul_a ", %%" _lt_clmul_b "\n" \
\
"pshufb %%" VR0(r) ",%%" _lt_mod_a "\n" \
"pshufb %%" VR1(r) ",%%" _lt_mod_b "\n" \
"pshufb %%" VR0(r) ",%%" _lt_clmul_a "\n" \
"pshufb %%" VR1(r) ",%%" _lt_clmul_b "\n" \
\
"pxor %%" _lt_mod_a ",%%" _lt_clmul_a "\n" \
"pxor %%" _lt_mod_b ",%%" _lt_clmul_b "\n" \
"movdqa %%" _lt_clmul_a ",%%" VR0(r) "\n" \
"movdqa %%" _lt_clmul_b ",%%" VR1(r) "\n" \
/* lts for lower part */ \
"movdqa 0x20(%[lt]), %%" _lt_mod_a "\n" \
"movdqa 0x30(%[lt]), %%" _lt_clmul_a "\n" \
"movdqa %%" _lt_mod_a ", %%" _lt_mod_b "\n" \
"movdqa %%" _lt_clmul_a ", %%" _lt_clmul_b "\n" \
/* lower part */ \
"pshufb %%" _a_save ",%%" _lt_mod_a "\n" \
"pshufb %%" _b_save ",%%" _lt_mod_b "\n" \
"pshufb %%" _a_save ",%%" _lt_clmul_a "\n" \
"pshufb %%" _b_save ",%%" _lt_clmul_b "\n" \
\
"pxor %%" _lt_mod_a ",%%" VR0(r) "\n" \
"pxor %%" _lt_mod_b ",%%" VR1(r) "\n" \
"pxor %%" _lt_clmul_a ",%%" VR0(r) "\n" \
"pxor %%" _lt_clmul_b ",%%" VR1(r) "\n" \
: : [mask] "r" (0x0f0f0f0f), \
[lt] "r" (gf_clmul_mod_lt[4*(c)])); \
break; \
default: \
ASM_BUG(); \
} \
}
#define MUL(c, r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
_MULx2(c, R_23(r)); \
_MULx2(c, R_01(r)); \
break; \
case 2: \
_MULx2(c, R_01(r)); \
break; \
default: \
ASM_BUG(); \
} \
}
#define raidz_math_begin() kfpu_begin()
#define raidz_math_end() kfpu_end()
#define GEN_P_DEFINE() {}
#define GEN_P_STRIDE 4
#define GEN_P_P 0, 1, 2, 3
#define GEN_PQ_DEFINE() {}
#define GEN_PQ_STRIDE 4
#define GEN_PQ_D 0, 1, 2, 3
#define GEN_PQ_P 4, 5, 6, 7
#define GEN_PQ_Q 8, 9, 10, 11
#define GEN_PQR_DEFINE() {}
#define GEN_PQR_STRIDE 2
#define GEN_PQR_D 0, 1
#define GEN_PQR_P 2, 3
#define GEN_PQR_Q 4, 5
#define GEN_PQR_R 6, 7
#define REC_P_DEFINE() {}
#define REC_P_STRIDE 4
#define REC_P_X 0, 1, 2, 3
#define REC_Q_DEFINE() {}
#define REC_Q_STRIDE 4
#define REC_Q_X 0, 1, 2, 3
#define REC_R_DEFINE() {}
#define REC_R_STRIDE 4
#define REC_R_X 0, 1, 2, 3
#define REC_PQ_DEFINE() {}
#define REC_PQ_STRIDE 2
#define REC_PQ_X 0, 1
#define REC_PQ_Y 2, 3
#define REC_PQ_D 4, 5
#define REC_PR_DEFINE() {}
#define REC_PR_STRIDE 2
#define REC_PR_X 0, 1
#define REC_PR_Y 2, 3
#define REC_PR_D 4, 5
#define REC_QR_DEFINE() {}
#define REC_QR_STRIDE 2
#define REC_QR_X 0, 1
#define REC_QR_Y 2, 3
#define REC_QR_D 4, 5
#define REC_PQR_DEFINE() {}
#define REC_PQR_STRIDE 2
#define REC_PQR_X 0, 1
#define REC_PQR_Y 2, 3
#define REC_PQR_Z 4, 5
#define REC_PQR_D 6, 7
#define REC_PQR_XS 6, 7
#define REC_PQR_YS 8, 9
#include <sys/vdev_raidz_impl.h>
#include "vdev_raidz_math_impl.h"
DEFINE_GEN_METHODS(ssse3);
DEFINE_REC_METHODS(ssse3);
static boolean_t
raidz_will_ssse3_work(void)
{
return (zfs_sse_available() && zfs_sse2_available() &&
zfs_ssse3_available());
}
const raidz_impl_ops_t vdev_raidz_ssse3_impl = {
.init = NULL,
.fini = NULL,
.gen = RAIDZ_GEN_METHODS(ssse3),
.rec = RAIDZ_REC_METHODS(ssse3),
.is_supported = &raidz_will_ssse3_work,
.name = "ssse3"
};
#endif /* defined(__x86_64) && defined(HAVE_SSSE3) */
#if defined(__x86_64) && (defined(HAVE_SSSE3) || defined(HAVE_AVX2))
const uint8_t
__attribute__((aligned(256))) gf_clmul_mod_lt[4*256][16] = {
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
0x80, 0x90, 0xa0, 0xb0, 0xc0, 0xd0, 0xe0, 0xf0 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
{ 0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0,
0x00, 0x20, 0x40, 0x60, 0x80, 0xa0, 0xc0, 0xe0 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d },
{ 0x00, 0x30, 0x60, 0x50, 0xc0, 0xf0, 0xa0, 0x90,
0x80, 0xb0, 0xe0, 0xd0, 0x40, 0x70, 0x20, 0x10 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x03, 0x06, 0x05, 0x0c, 0x0f, 0x0a, 0x09,
0x18, 0x1b, 0x1e, 0x1d, 0x14, 0x17, 0x12, 0x11 },
{ 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d,
0x3a, 0x3a, 0x3a, 0x3a, 0x27, 0x27, 0x27, 0x27 },
{ 0x00, 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0,
0x00, 0x40, 0x80, 0xc0, 0x00, 0x40, 0x80, 0xc0 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
0x20, 0x24, 0x28, 0x2c, 0x30, 0x34, 0x38, 0x3c },
{ 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d,
0x3a, 0x3a, 0x3a, 0x3a, 0x27, 0x27, 0x27, 0x27 },
{ 0x00, 0x50, 0xa0, 0xf0, 0x40, 0x10, 0xe0, 0xb0,
0x80, 0xd0, 0x20, 0x70, 0xc0, 0x90, 0x60, 0x30 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x11, 0x1e, 0x1b,
0x28, 0x2d, 0x22, 0x27, 0x3c, 0x39, 0x36, 0x33 },
{ 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d,
0x27, 0x27, 0x27, 0x27, 0x3a, 0x3a, 0x3a, 0x3a },
{ 0x00, 0x60, 0xc0, 0xa0, 0x80, 0xe0, 0x40, 0x20,
0x00, 0x60, 0xc0, 0xa0, 0x80, 0xe0, 0x40, 0x20 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x06, 0x0c, 0x0a, 0x18, 0x1e, 0x14, 0x12,
0x30, 0x36, 0x3c, 0x3a, 0x28, 0x2e, 0x24, 0x22 },
{ 0x00, 0x00, 0x00, 0x00, 0x1d, 0x1d, 0x1d, 0x1d,
0x27, 0x27, 0x27, 0x27, 0x3a, 0x3a, 0x3a, 0x3a },
{ 0x00, 0x70, 0xe0, 0x90, 0xc0, 0xb0, 0x20, 0x50,
0x80, 0xf0, 0x60, 0x10, 0x40, 0x30, 0xa0, 0xd0 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d },
{ 0x00, 0x00, 0x1d, 0x1d, 0x3a, 0x3a, 0x27, 0x27,
0x74, 0x74, 0x69, 0x69, 0x4e, 0x4e, 0x53, 0x53 },
{ 0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80,
0x00, 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, 0x80 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, 0x38,
0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78 },
{ 0x00, 0x00, 0x1d, 0x1d, 0x3a, 0x3a, 0x27, 0x27,
0x74, 0x74, 0x69, 0x69, 0x4e, 0x4e, 0x53, 0x53 },
{ 0x00, 0x90, 0x20, 0xb0, 0x40, 0xd0, 0x60, 0xf0,
0x80, 0x10, 0xa0, 0x30, 0xc0, 0x50, 0xe0, 0x70 },
{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
{ 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77 },
{ 0x00, 0x00, 0x1d, 0x1d, 0x3a, 0x3a, 0x27, 0x27,
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{ 0x00, 0xfc, 0xf8, 0x04, 0xf0, 0x0c, 0x08, 0xf4,
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{ 0x00, 0xfd, 0xfa, 0x07, 0xf4, 0x09, 0x0e, 0xf3,
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{ 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
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{ 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
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{ 0x00, 0xfe, 0xfc, 0x02, 0xf8, 0x06, 0x04, 0xfa,
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{ 0x00, 0xbb, 0x76, 0xcd, 0xf1, 0x4a, 0x87, 0x3c,
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{ 0x00, 0xf0, 0xe0, 0x10, 0xc0, 0x30, 0x20, 0xd0,
0x80, 0x70, 0x60, 0x90, 0x40, 0xb0, 0xa0, 0x50 },
{ 0x00, 0x00, 0x1d, 0x1d, 0x27, 0x27, 0x3a, 0x3a,
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{ 0x00, 0xff, 0xfe, 0x01, 0xfc, 0x03, 0x02, 0xfd,
0xf8, 0x07, 0x06, 0xf9, 0x04, 0xfb, 0xfa, 0x05 }
};
#endif /* defined(__x86_64) && (defined(HAVE_SSSE3) || defined(HAVE_AVX2)) */
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