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65d71d4212
Implement shift based multiplication for 512f. Higher IPC over lookup based methods yields up to 40% better performance on the current hardware. Results on Xeon Phi(TM) CPU 7210: implementation gen_p gen_pq gen_pqr rec_p rec_q rec_r rec_pq rec_pr rec_qr rec_pqr original 142232671 24411492 12948205 283053705 22348167 4215911 9171609 2265548 2378370 1648495 scalar 295711162 49851491 33253815 293198109 88179448 61866752 27941684 25764416 17384442 12138153 sse2 410055998 199642658 117973654 406240463 152688682 121092250 84968180 79291076 47473657 20779719 ssse3 411641595 199669571 117937647 406211024 137638508 117050346 81263322 76120405 46281559 32696722 avx2 616485806 311515332 188595628 605455115 260602390 230554476 148198817 138800254 92273356 62937819 avx512f 832191523 408509425 253599522 810094481 404325734 317590971 218235687 197204920 133101937 94001219 fastest avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f avx512f Signed-off-by: Gvozden Neskovic <neskovic@gmail.com>
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Nešković. All rights reserved.
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*/
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#include <sys/isa_defs.h>
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#if defined(__x86_64) && defined(HAVE_AVX2)
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#include <sys/types.h>
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#include <linux/simd_x86.h>
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#define __asm __asm__ __volatile__
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#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
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#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
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#define VR0_(REG, ...) "ymm"#REG
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#define VR1_(_1, REG, ...) "ymm"#REG
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#define VR2_(_1, _2, REG, ...) "ymm"#REG
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#define VR3_(_1, _2, _3, REG, ...) "ymm"#REG
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#define VR4_(_1, _2, _3, _4, REG, ...) "ymm"#REG
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#define VR5_(_1, _2, _3, _4, _5, REG, ...) "ymm"#REG
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#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "ymm"#REG
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#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "ymm"#REG
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#define VR0(r...) VR0_(r)
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#define VR1(r...) VR1_(r)
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#define VR2(r...) VR2_(r, 1)
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#define VR3(r...) VR3_(r, 1, 2)
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#define VR4(r...) VR4_(r, 1, 2)
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#define VR5(r...) VR5_(r, 1, 2, 3)
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#define VR6(r...) VR6_(r, 1, 2, 3, 4)
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#define VR7(r...) VR7_(r, 1, 2, 3, 4, 5)
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#define R_01(REG1, REG2, ...) REG1, REG2
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#define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3
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#define R_23(REG...) _R_23(REG, 1, 2, 3)
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#define ASM_BUG() ASSERT(0)
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extern const uint8_t gf_clmul_mod_lt[4*256][16];
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#define ELEM_SIZE 32
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typedef struct v {
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uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
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} v_t;
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#define XOR_ACC(src, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
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"vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
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"vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
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"vpxor 0x60(%[SRC]), %%" VR3(r)", %%" VR3(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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case 2: \
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__asm( \
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"vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
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"vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define XOR(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 8: \
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__asm( \
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"vpxor %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n" \
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"vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
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"vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
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"vpxor %" VR3(r) ", %" VR7(r)", %" VR7(r)); \
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break; \
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case 4: \
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__asm( \
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"vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
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"vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define ZERO(r...) XOR(r, r)
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#define COPY(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 8: \
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__asm( \
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"vmovdqa %" VR0(r) ", %" VR4(r) "\n" \
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"vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
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"vmovdqa %" VR2(r) ", %" VR6(r) "\n" \
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"vmovdqa %" VR3(r) ", %" VR7(r)); \
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break; \
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case 4: \
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__asm( \
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"vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
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"vmovdqa %" VR1(r) ", %" VR3(r)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define LOAD(src, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
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"vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
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"vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n" \
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"vmovdqa 0x60(%[SRC]), %%" VR3(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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case 2: \
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__asm( \
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"vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
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"vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define STORE(dst, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vmovdqa %%" VR0(r) ", 0x00(%[DST])\n" \
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"vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
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"vmovdqa %%" VR2(r) ", 0x40(%[DST])\n" \
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"vmovdqa %%" VR3(r) ", 0x60(%[DST])\n" \
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: : [DST] "r" (dst)); \
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break; \
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case 2: \
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__asm( \
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"vmovdqa %%" VR0(r) ", 0x00(%[DST])\n" \
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"vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
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: : [DST] "r" (dst)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define FLUSH() \
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{ \
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__asm("vzeroupper"); \
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}
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#define MUL2_SETUP() \
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{ \
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__asm("vmovq %0, %%xmm14" :: "r"(0x1d1d1d1d1d1d1d1d)); \
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__asm("vpbroadcastq %xmm14, %ymm14"); \
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__asm("vpxor %ymm15, %ymm15 ,%ymm15"); \
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}
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#define _MUL2(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 2: \
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__asm( \
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"vpcmpgtb %" VR0(r)", %ymm15, %ymm12\n" \
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"vpcmpgtb %" VR1(r)", %ymm15, %ymm13\n" \
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"vpaddb %" VR0(r)", %" VR0(r)", %" VR0(r) "\n" \
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"vpaddb %" VR1(r)", %" VR1(r)", %" VR1(r) "\n" \
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"vpand %ymm14, %ymm12, %ymm12\n" \
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"vpand %ymm14, %ymm13, %ymm13\n" \
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"vpxor %ymm12, %" VR0(r)", %" VR0(r) "\n" \
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"vpxor %ymm13, %" VR1(r)", %" VR1(r)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define MUL2(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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_MUL2(R_01(r)); \
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_MUL2(R_23(r)); \
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break; \
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case 2: \
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_MUL2(r); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define MUL4(r...) \
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{ \
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MUL2(r); \
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MUL2(r); \
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}
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#define _0f "ymm15"
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#define _as "ymm14"
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#define _bs "ymm13"
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#define _ltmod "ymm12"
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#define _ltmul "ymm11"
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#define _ta "ymm10"
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#define _tb "ymm15"
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static const uint8_t __attribute__((aligned(32))) _mul_mask = 0x0F;
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#define _MULx2(c, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 2: \
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__asm( \
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"vpbroadcastb (%[mask]), %%" _0f "\n" \
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/* upper bits */ \
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"vbroadcasti128 0x00(%[lt]), %%" _ltmod "\n" \
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"vbroadcasti128 0x10(%[lt]), %%" _ltmul "\n" \
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\
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"vpsraw $0x4, %%" VR0(r) ", %%"_as "\n" \
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"vpsraw $0x4, %%" VR1(r) ", %%"_bs "\n" \
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"vpand %%" _0f ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpand %%" _0f ", %%" VR1(r) ", %%" VR1(r) "\n" \
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"vpand %%" _0f ", %%" _as ", %%" _as "\n" \
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"vpand %%" _0f ", %%" _bs ", %%" _bs "\n" \
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\
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"vpshufb %%" _as ", %%" _ltmod ", %%" _ta "\n" \
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"vpshufb %%" _bs ", %%" _ltmod ", %%" _tb "\n" \
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"vpshufb %%" _as ", %%" _ltmul ", %%" _as "\n" \
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"vpshufb %%" _bs ", %%" _ltmul ", %%" _bs "\n" \
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/* lower bits */ \
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"vbroadcasti128 0x20(%[lt]), %%" _ltmod "\n" \
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"vbroadcasti128 0x30(%[lt]), %%" _ltmul "\n" \
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\
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"vpxor %%" _ta ", %%" _as ", %%" _as "\n" \
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"vpxor %%" _tb ", %%" _bs ", %%" _bs "\n" \
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\
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"vpshufb %%" VR0(r) ", %%" _ltmod ", %%" _ta "\n" \
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"vpshufb %%" VR1(r) ", %%" _ltmod ", %%" _tb "\n" \
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"vpshufb %%" VR0(r) ", %%" _ltmul ", %%" VR0(r) "\n"\
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"vpshufb %%" VR1(r) ", %%" _ltmul ", %%" VR1(r) "\n"\
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\
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"vpxor %%" _ta ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpxor %%" _as ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpxor %%" _tb ", %%" VR1(r) ", %%" VR1(r) "\n" \
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"vpxor %%" _bs ", %%" VR1(r) ", %%" VR1(r) "\n" \
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: : [mask] "r" (&_mul_mask), \
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[lt] "r" (gf_clmul_mod_lt[4*(c)])); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define MUL(c, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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_MULx2(c, R_01(r)); \
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_MULx2(c, R_23(r)); \
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break; \
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case 2: \
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_MULx2(c, R_01(r)); \
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break; \
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default: \
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ASM_BUG(); \
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} \
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}
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#define raidz_math_begin() kfpu_begin()
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#define raidz_math_end() \
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{ \
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FLUSH(); \
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kfpu_end(); \
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}
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#define SYN_STRIDE 4
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#define ZERO_STRIDE 4
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#define ZERO_DEFINE() {}
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#define ZERO_D 0, 1, 2, 3
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#define COPY_STRIDE 4
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#define COPY_DEFINE() {}
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#define COPY_D 0, 1, 2, 3
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#define ADD_STRIDE 4
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#define ADD_DEFINE() {}
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#define ADD_D 0, 1, 2, 3
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#define MUL_STRIDE 4
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#define MUL_DEFINE() {}
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#define MUL_D 0, 1, 2, 3
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#define GEN_P_STRIDE 4
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#define GEN_P_DEFINE() {}
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#define GEN_P_P 0, 1, 2, 3
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#define GEN_PQ_STRIDE 4
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#define GEN_PQ_DEFINE() {}
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#define GEN_PQ_D 0, 1, 2, 3
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#define GEN_PQ_C 4, 5, 6, 7
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#define GEN_PQR_STRIDE 4
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#define GEN_PQR_DEFINE() {}
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#define GEN_PQR_D 0, 1, 2, 3
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#define GEN_PQR_C 4, 5, 6, 7
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#define SYN_Q_DEFINE() {}
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#define SYN_Q_D 0, 1, 2, 3
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#define SYN_Q_X 4, 5, 6, 7
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#define SYN_R_DEFINE() {}
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#define SYN_R_D 0, 1, 2, 3
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#define SYN_R_X 4, 5, 6, 7
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#define SYN_PQ_DEFINE() {}
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#define SYN_PQ_D 0, 1, 2, 3
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#define SYN_PQ_X 4, 5, 6, 7
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#define REC_PQ_STRIDE 2
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#define REC_PQ_DEFINE() {}
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#define REC_PQ_X 0, 1
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#define REC_PQ_Y 2, 3
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#define REC_PQ_T 4, 5
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#define SYN_PR_DEFINE() {}
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#define SYN_PR_D 0, 1, 2, 3
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#define SYN_PR_X 4, 5, 6, 7
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#define REC_PR_STRIDE 2
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#define REC_PR_DEFINE() {}
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#define REC_PR_X 0, 1
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#define REC_PR_Y 2, 3
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#define REC_PR_T 4, 5
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#define SYN_QR_DEFINE() {}
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#define SYN_QR_D 0, 1, 2, 3
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#define SYN_QR_X 4, 5, 6, 7
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#define REC_QR_STRIDE 2
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#define REC_QR_DEFINE() {}
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#define REC_QR_X 0, 1
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#define REC_QR_Y 2, 3
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#define REC_QR_T 4, 5
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#define SYN_PQR_DEFINE() {}
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#define SYN_PQR_D 0, 1, 2, 3
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#define SYN_PQR_X 4, 5, 6, 7
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#define REC_PQR_STRIDE 2
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#define REC_PQR_DEFINE() {}
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#define REC_PQR_X 0, 1
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#define REC_PQR_Y 2, 3
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#define REC_PQR_Z 4, 5
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#define REC_PQR_XS 6, 7
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#define REC_PQR_YS 8, 9
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#include <sys/vdev_raidz_impl.h>
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#include "vdev_raidz_math_impl.h"
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DEFINE_GEN_METHODS(avx2);
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DEFINE_REC_METHODS(avx2);
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static boolean_t
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raidz_will_avx2_work(void)
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{
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return (zfs_avx_available() && zfs_avx2_available());
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}
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const raidz_impl_ops_t vdev_raidz_avx2_impl = {
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.init = NULL,
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.fini = NULL,
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.gen = RAIDZ_GEN_METHODS(avx2),
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.rec = RAIDZ_REC_METHODS(avx2),
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.is_supported = &raidz_will_avx2_work,
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.name = "avx2"
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};
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#endif /* defined(__x86_64) && defined(HAVE_AVX2) */
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