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02730c333c
Enable picky cstyle checks and resolve the new warnings. The vast
majority of the changes needed were to handle minor issues with
whitespace formatting. This patch contains no functional changes.
Non-whitespace changes are as follows:
* 8 times ; to { } in for/while loop
* fix missing ; in cmd/zed/agents/zfs_diagnosis.c
* comment (confim -> confirm)
* change endline , to ; in cmd/zpool/zpool_main.c
* a number of /* BEGIN CSTYLED */ /* END CSTYLED */ blocks
* /* CSTYLED */ markers
* change == 0 to !
* ulong to unsigned long in module/zfs/dsl_scan.c
* rearrangement of module_param lines in module/zfs/metaslab.c
* add { } block around statement after for_each_online_node
Reviewed-by: Giuseppe Di Natale <dinatale2@llnl.gov>
Reviewed-by: Håkan Johansson <f96hajo@chalmers.se>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #5465
610 lines
14 KiB
C
610 lines
14 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Neskovic <neskovic@compeng.uni-frankfurt.de>.
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*/
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/*
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* USER API:
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*
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* Kernel fpu methods:
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* kfpu_begin()
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* kfpu_end()
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*
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* SIMD support:
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*
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* Following functions should be called to determine whether CPU feature
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* is supported. All functions are usable in kernel and user space.
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* If a SIMD algorithm is using more than one instruction set
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* all relevant feature test functions should be called.
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*
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* Supported features:
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* zfs_sse_available()
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* zfs_sse2_available()
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* zfs_sse3_available()
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* zfs_ssse3_available()
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* zfs_sse4_1_available()
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* zfs_sse4_2_available()
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*
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* zfs_avx_available()
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* zfs_avx2_available()
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*
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* zfs_bmi1_available()
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* zfs_bmi2_available()
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*
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* zfs_avx512f_available()
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* zfs_avx512cd_available()
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* zfs_avx512er_available()
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* zfs_avx512pf_available()
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* zfs_avx512bw_available()
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* zfs_avx512dq_available()
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* zfs_avx512vl_available()
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* zfs_avx512ifma_available()
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* zfs_avx512vbmi_available()
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*
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* NOTE(AVX-512VL): If using AVX-512 instructions with 128Bit registers
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* also add zfs_avx512vl_available() to feature check.
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*/
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#ifndef _SIMD_X86_H
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#define _SIMD_X86_H
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#include <sys/isa_defs.h>
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/* only for __x86 */
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#if defined(__x86)
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#include <sys/types.h>
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#if defined(_KERNEL)
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#include <asm/cpufeature.h>
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#else
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#include <cpuid.h>
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#endif
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#if defined(_KERNEL)
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#if defined(HAVE_FPU_API_H)
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#include <asm/fpu/api.h>
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#include <asm/fpu/internal.h>
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#define kfpu_begin() \
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{ \
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preempt_disable(); \
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__kernel_fpu_begin(); \
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}
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#define kfpu_end() \
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{ \
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__kernel_fpu_end(); \
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preempt_enable(); \
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}
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#else
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#include <asm/i387.h>
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#include <asm/xcr.h>
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#define kfpu_begin() kernel_fpu_begin()
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#define kfpu_end() kernel_fpu_end()
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#endif /* defined(HAVE_FPU_API_H) */
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#else
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/*
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* fpu dummy methods for userspace
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*/
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#define kfpu_begin() do {} while (0)
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#define kfpu_end() do {} while (0)
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#endif /* defined(_KERNEL) */
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/*
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* CPUID feature tests for user-space. Linux kernel provides an interface for
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* CPU feature testing.
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*/
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#if !defined(_KERNEL)
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/*
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* x86 registers used implicitly by CPUID
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*/
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typedef enum cpuid_regs {
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EAX = 0,
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EBX,
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ECX,
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EDX,
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CPUID_REG_CNT = 4
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} cpuid_regs_t;
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/*
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* List of instruction sets identified by CPUID
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*/
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typedef enum cpuid_inst_sets {
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SSE = 0,
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SSE2,
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SSE3,
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SSSE3,
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SSE4_1,
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SSE4_2,
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OSXSAVE,
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AVX,
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AVX2,
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BMI1,
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BMI2,
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AVX512F,
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AVX512CD,
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AVX512DQ,
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AVX512BW,
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AVX512IFMA,
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AVX512VBMI,
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AVX512PF,
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AVX512ER,
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AVX512VL
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} cpuid_inst_sets_t;
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/*
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* Instruction set descriptor.
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*/
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typedef struct cpuid_feature_desc {
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uint32_t leaf; /* CPUID leaf */
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uint32_t subleaf; /* CPUID sub-leaf */
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uint32_t flag; /* bit mask of the feature */
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cpuid_regs_t reg; /* which CPUID return register to test */
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} cpuid_feature_desc_t;
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#define _AVX512F_BIT (1U << 16)
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#define _AVX512CD_BIT (_AVX512F_BIT | (1U << 28))
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#define _AVX512DQ_BIT (_AVX512F_BIT | (1U << 17))
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#define _AVX512BW_BIT (_AVX512F_BIT | (1U << 30))
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#define _AVX512IFMA_BIT (_AVX512F_BIT | (1U << 21))
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#define _AVX512VBMI_BIT (1U << 1) /* AVX512F_BIT is on another leaf */
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#define _AVX512PF_BIT (_AVX512F_BIT | (1U << 26))
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#define _AVX512ER_BIT (_AVX512F_BIT | (1U << 27))
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#define _AVX512VL_BIT (1U << 31) /* if used also check other levels */
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/*
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* Descriptions of supported instruction sets
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*/
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static const cpuid_feature_desc_t cpuid_features[] = {
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[SSE] = {1U, 0U, 1U << 25, EDX },
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[SSE2] = {1U, 0U, 1U << 26, EDX },
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[SSE3] = {1U, 0U, 1U << 0, ECX },
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[SSSE3] = {1U, 0U, 1U << 9, ECX },
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[SSE4_1] = {1U, 0U, 1U << 19, ECX },
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[SSE4_2] = {1U, 0U, 1U << 20, ECX },
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[OSXSAVE] = {1U, 0U, 1U << 27, ECX },
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[AVX] = {1U, 0U, 1U << 28, ECX },
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[AVX2] = {7U, 0U, 1U << 5, EBX },
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[BMI1] = {7U, 0U, 1U << 3, EBX },
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[BMI2] = {7U, 0U, 1U << 8, EBX },
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[AVX512F] = {7U, 0U, _AVX512F_BIT, EBX },
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[AVX512CD] = {7U, 0U, _AVX512CD_BIT, EBX },
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[AVX512DQ] = {7U, 0U, _AVX512DQ_BIT, EBX },
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[AVX512BW] = {7U, 0U, _AVX512BW_BIT, EBX },
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[AVX512IFMA] = {7U, 0U, _AVX512IFMA_BIT, EBX },
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[AVX512VBMI] = {7U, 0U, _AVX512VBMI_BIT, ECX },
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[AVX512PF] = {7U, 0U, _AVX512PF_BIT, EBX },
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[AVX512ER] = {7U, 0U, _AVX512ER_BIT, EBX },
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[AVX512VL] = {7U, 0U, _AVX512ER_BIT, EBX }
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};
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/*
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* Check if OS supports AVX and AVX2 by checking XCR0
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* Only call this function if CPUID indicates that AVX feature is
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* supported by the CPU, otherwise it might be an illegal instruction.
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*/
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static inline uint64_t
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xgetbv(uint32_t index)
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{
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uint32_t eax, edx;
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/* xgetbv - instruction byte code */
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__asm__ __volatile__(".byte 0x0f; .byte 0x01; .byte 0xd0"
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: "=a" (eax), "=d" (edx)
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: "c" (index));
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return ((((uint64_t)edx)<<32) | (uint64_t)eax);
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}
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/*
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* Check if CPU supports a feature
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*/
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static inline boolean_t
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__cpuid_check_feature(const cpuid_feature_desc_t *desc)
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{
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uint32_t r[CPUID_REG_CNT];
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if (__get_cpuid_max(0, NULL) >= desc->leaf) {
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/*
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* __cpuid_count is needed to properly check
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* for AVX2. It is a macro, so return parameters
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* are passed by value.
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*/
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__cpuid_count(desc->leaf, desc->subleaf,
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r[EAX], r[EBX], r[ECX], r[EDX]);
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return ((r[desc->reg] & desc->flag) == desc->flag);
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}
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return (B_FALSE);
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}
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#define CPUID_FEATURE_CHECK(name, id) \
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static inline boolean_t \
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__cpuid_has_ ## name(void) \
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{ \
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return (__cpuid_check_feature(&cpuid_features[id])); \
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}
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/*
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* Define functions for user-space CPUID features testing
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*/
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CPUID_FEATURE_CHECK(sse, SSE);
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CPUID_FEATURE_CHECK(sse2, SSE2);
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CPUID_FEATURE_CHECK(sse3, SSE3);
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CPUID_FEATURE_CHECK(ssse3, SSSE3);
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CPUID_FEATURE_CHECK(sse4_1, SSE4_1);
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CPUID_FEATURE_CHECK(sse4_2, SSE4_2);
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CPUID_FEATURE_CHECK(avx, AVX);
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CPUID_FEATURE_CHECK(avx2, AVX2);
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CPUID_FEATURE_CHECK(osxsave, OSXSAVE);
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CPUID_FEATURE_CHECK(bmi1, BMI1);
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CPUID_FEATURE_CHECK(bmi2, BMI2);
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CPUID_FEATURE_CHECK(avx512f, AVX512F);
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CPUID_FEATURE_CHECK(avx512cd, AVX512CD);
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CPUID_FEATURE_CHECK(avx512dq, AVX512DQ);
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CPUID_FEATURE_CHECK(avx512bw, AVX512BW);
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CPUID_FEATURE_CHECK(avx512ifma, AVX512IFMA);
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CPUID_FEATURE_CHECK(avx512vbmi, AVX512VBMI);
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CPUID_FEATURE_CHECK(avx512pf, AVX512PF);
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CPUID_FEATURE_CHECK(avx512er, AVX512ER);
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CPUID_FEATURE_CHECK(avx512vl, AVX512VL);
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#endif /* !defined(_KERNEL) */
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/*
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* Detect register set support
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*/
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static inline boolean_t
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__simd_state_enabled(const uint64_t state)
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{
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boolean_t has_osxsave;
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uint64_t xcr0;
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#if defined(_KERNEL) && defined(X86_FEATURE_OSXSAVE)
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has_osxsave = !!boot_cpu_has(X86_FEATURE_OSXSAVE);
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#elif defined(_KERNEL) && !defined(X86_FEATURE_OSXSAVE)
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has_osxsave = B_FALSE;
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#else
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has_osxsave = __cpuid_has_osxsave();
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#endif
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if (!has_osxsave)
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return (B_FALSE);
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xcr0 = xgetbv(0);
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return ((xcr0 & state) == state);
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}
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#define _XSTATE_SSE_AVX (0x2 | 0x4)
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#define _XSTATE_AVX512 (0xE0 | _XSTATE_SSE_AVX)
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#define __ymm_enabled() __simd_state_enabled(_XSTATE_SSE_AVX)
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#define __zmm_enabled() __simd_state_enabled(_XSTATE_AVX512)
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/*
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* Check if SSE instruction set is available
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*/
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static inline boolean_t
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zfs_sse_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_XMM));
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#else
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return (__cpuid_has_sse());
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#endif
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}
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/*
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* Check if SSE2 instruction set is available
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*/
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static inline boolean_t
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zfs_sse2_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_XMM2));
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#else
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return (__cpuid_has_sse2());
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#endif
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}
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/*
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* Check if SSE3 instruction set is available
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*/
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static inline boolean_t
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zfs_sse3_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_XMM3));
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#else
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return (__cpuid_has_sse3());
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#endif
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}
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/*
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* Check if SSSE3 instruction set is available
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*/
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static inline boolean_t
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zfs_ssse3_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_SSSE3));
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#else
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return (__cpuid_has_ssse3());
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#endif
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}
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/*
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* Check if SSE4.1 instruction set is available
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*/
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static inline boolean_t
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zfs_sse4_1_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_XMM4_1));
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#else
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return (__cpuid_has_sse4_1());
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#endif
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}
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/*
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* Check if SSE4.2 instruction set is available
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*/
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static inline boolean_t
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zfs_sse4_2_available(void)
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{
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#if defined(_KERNEL)
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return (!!boot_cpu_has(X86_FEATURE_XMM4_2));
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#else
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return (__cpuid_has_sse4_2());
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#endif
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}
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/*
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* Check if AVX instruction set is available
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*/
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static inline boolean_t
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zfs_avx_available(void)
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{
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boolean_t has_avx;
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#if defined(_KERNEL)
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has_avx = !!boot_cpu_has(X86_FEATURE_AVX);
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#else
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has_avx = __cpuid_has_avx();
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#endif
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return (has_avx && __ymm_enabled());
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}
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/*
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* Check if AVX2 instruction set is available
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*/
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static inline boolean_t
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zfs_avx2_available(void)
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{
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boolean_t has_avx2;
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#if defined(_KERNEL) && defined(X86_FEATURE_AVX2)
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has_avx2 = !!boot_cpu_has(X86_FEATURE_AVX2);
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#elif defined(_KERNEL) && !defined(X86_FEATURE_AVX2)
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has_avx2 = B_FALSE;
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#else
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has_avx2 = __cpuid_has_avx2();
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#endif
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return (has_avx2 && __ymm_enabled());
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}
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/*
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* Check if BMI1 instruction set is available
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*/
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static inline boolean_t
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zfs_bmi1_available(void)
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{
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#if defined(_KERNEL) && defined(X86_FEATURE_BMI1)
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return (!!boot_cpu_has(X86_FEATURE_BMI1));
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#elif defined(_KERNEL) && !defined(X86_FEATURE_BMI1)
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return (B_FALSE);
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#else
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return (__cpuid_has_bmi1());
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#endif
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}
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/*
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* Check if BMI2 instruction set is available
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*/
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static inline boolean_t
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zfs_bmi2_available(void)
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{
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#if defined(_KERNEL) && defined(X86_FEATURE_BMI2)
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return (!!boot_cpu_has(X86_FEATURE_BMI2));
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#elif defined(_KERNEL) && !defined(X86_FEATURE_BMI2)
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return (B_FALSE);
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#else
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return (__cpuid_has_bmi2());
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#endif
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}
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/*
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* AVX-512 family of instruction sets:
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*
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* AVX512F Foundation
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* AVX512CD Conflict Detection Instructions
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* AVX512ER Exponential and Reciprocal Instructions
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* AVX512PF Prefetch Instructions
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*
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* AVX512BW Byte and Word Instructions
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* AVX512DQ Double-word and Quadword Instructions
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* AVX512VL Vector Length Extensions
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*
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* AVX512IFMA Integer Fused Multiply Add (Not supported by kernel 4.4)
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* AVX512VBMI Vector Byte Manipulation Instructions
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*/
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/* Check if AVX512F instruction set is available */
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static inline boolean_t
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zfs_avx512f_available(void)
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{
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boolean_t has_avx512 = B_FALSE;
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#if defined(_KERNEL) && defined(X86_FEATURE_AVX512F)
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has_avx512 = !!boot_cpu_has(X86_FEATURE_AVX512F);
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#elif !defined(_KERNEL)
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has_avx512 = __cpuid_has_avx512f();
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#endif
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return (has_avx512 && __zmm_enabled());
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}
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/* Check if AVX512CD instruction set is available */
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static inline boolean_t
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zfs_avx512cd_available(void)
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{
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boolean_t has_avx512 = B_FALSE;
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#if defined(_KERNEL) && defined(X86_FEATURE_AVX512CD)
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has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512CD);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512cd();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512ER instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512er_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512ER)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512ER);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512er();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512PF instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512pf_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512PF)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512PF);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512pf();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512BW instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512bw_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512BW)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512BW);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512bw();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512DQ instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512dq_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512DQ)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512DQ);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512dq();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512VL instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512vl_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512VL)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512VL);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512vl();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512IFMA instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512ifma_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512IFMA)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512IFMA);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512ifma();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
/* Check if AVX512VBMI instruction set is available */
|
|
static inline boolean_t
|
|
zfs_avx512vbmi_available(void)
|
|
{
|
|
boolean_t has_avx512 = B_FALSE;
|
|
|
|
#if defined(_KERNEL) && defined(X86_FEATURE_AVX512VBMI)
|
|
has_avx512 = boot_cpu_has(X86_FEATURE_AVX512F) &&
|
|
boot_cpu_has(X86_FEATURE_AVX512VBMI);
|
|
#elif !defined(_KERNEL)
|
|
has_avx512 = __cpuid_has_avx512f() &&
|
|
__cpuid_has_avx512vbmi();
|
|
#endif
|
|
|
|
return (has_avx512 && __zmm_enabled());
|
|
}
|
|
|
|
#endif /* defined(__x86) */
|
|
|
|
#endif /* _SIMD_X86_H */
|