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59493b63c1
When processing abds, we execute 1 `kfpu_begin()`/`kfpu_end()` pair on every page in the abd. This is wasteful and slows down checksum performance versus what the benchmark claimed. We correct this by moving those calls to the init and fini functions. Also, we always check the buffer length against 0 before calling the non-scalar checksum functions. This means that we do not need to execute the loop condition for the first loop iteration. That allows us to micro-optimize the checksum calculations by switching to do-while loops. Note that we do not apply that micro-optimization to the scalar implementation because there is no check in `fletcher_4_incremental_native()`/`fletcher_4_incremental_byteswap()` against 0 sized buffers being passed. Reviewed-by: Alexander Motin <mav@FreeBSD.org> Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Signed-off-by: Richard Yao <richard.yao@alumni.stonybrook.edu> Closes #14247
234 lines
6.9 KiB
C
234 lines
6.9 KiB
C
/*
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* Implement fast Fletcher4 using superscalar pipelines.
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*
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* Use regular C code to compute
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* Fletcher4 in four incremental 64-bit parallel accumulator streams,
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* and then combine the streams to form the final four checksum words.
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* This implementation is a derivative of the AVX SIMD implementation by
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* James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
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*
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* Copyright (C) 2016 Romain Dolbeau.
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*
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* Authors:
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* Romain Dolbeau <romain.dolbeau@atos.net>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <sys/param.h>
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#include <sys/byteorder.h>
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#include <sys/spa_checksum.h>
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#include <sys/string.h>
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#include <zfs_fletcher.h>
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_superscalar4_init(fletcher_4_ctx_t *ctx)
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{
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memset(ctx->superscalar, 0, 4 * sizeof (zfs_fletcher_superscalar_t));
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}
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_superscalar4_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
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{
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uint64_t A, B, C, D;
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A = ctx->superscalar[0].v[0] + ctx->superscalar[0].v[1] +
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ctx->superscalar[0].v[2] + ctx->superscalar[0].v[3];
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B = 0 - ctx->superscalar[0].v[1] - 2 * ctx->superscalar[0].v[2] -
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3 * ctx->superscalar[0].v[3] + 4 * ctx->superscalar[1].v[0] +
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4 * ctx->superscalar[1].v[1] + 4 * ctx->superscalar[1].v[2] +
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4 * ctx->superscalar[1].v[3];
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C = ctx->superscalar[0].v[2] + 3 * ctx->superscalar[0].v[3] -
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6 * ctx->superscalar[1].v[0] - 10 * ctx->superscalar[1].v[1] -
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14 * ctx->superscalar[1].v[2] - 18 * ctx->superscalar[1].v[3] +
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16 * ctx->superscalar[2].v[0] + 16 * ctx->superscalar[2].v[1] +
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16 * ctx->superscalar[2].v[2] + 16 * ctx->superscalar[2].v[3];
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D = 0 - ctx->superscalar[0].v[3] + 4 * ctx->superscalar[1].v[0] +
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10 * ctx->superscalar[1].v[1] + 20 * ctx->superscalar[1].v[2] +
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34 * ctx->superscalar[1].v[3] - 48 * ctx->superscalar[2].v[0] -
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64 * ctx->superscalar[2].v[1] - 80 * ctx->superscalar[2].v[2] -
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96 * ctx->superscalar[2].v[3] + 64 * ctx->superscalar[3].v[0] +
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64 * ctx->superscalar[3].v[1] + 64 * ctx->superscalar[3].v[2] +
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64 * ctx->superscalar[3].v[3];
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_superscalar4_native(fletcher_4_ctx_t *ctx,
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const void *buf, uint64_t size)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = ip + (size / sizeof (uint32_t));
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uint64_t a, b, c, d;
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uint64_t a2, b2, c2, d2;
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uint64_t a3, b3, c3, d3;
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uint64_t a4, b4, c4, d4;
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a = ctx->superscalar[0].v[0];
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b = ctx->superscalar[1].v[0];
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c = ctx->superscalar[2].v[0];
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d = ctx->superscalar[3].v[0];
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a2 = ctx->superscalar[0].v[1];
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b2 = ctx->superscalar[1].v[1];
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c2 = ctx->superscalar[2].v[1];
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d2 = ctx->superscalar[3].v[1];
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a3 = ctx->superscalar[0].v[2];
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b3 = ctx->superscalar[1].v[2];
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c3 = ctx->superscalar[2].v[2];
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d3 = ctx->superscalar[3].v[2];
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a4 = ctx->superscalar[0].v[3];
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b4 = ctx->superscalar[1].v[3];
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c4 = ctx->superscalar[2].v[3];
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d4 = ctx->superscalar[3].v[3];
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do {
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a += ip[0];
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a2 += ip[1];
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a3 += ip[2];
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a4 += ip[3];
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b += a;
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b2 += a2;
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b3 += a3;
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b4 += a4;
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c += b;
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c2 += b2;
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c3 += b3;
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c4 += b4;
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d += c;
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d2 += c2;
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d3 += c3;
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d4 += c4;
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} while ((ip += 4) < ipend);
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ctx->superscalar[0].v[0] = a;
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ctx->superscalar[1].v[0] = b;
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ctx->superscalar[2].v[0] = c;
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ctx->superscalar[3].v[0] = d;
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ctx->superscalar[0].v[1] = a2;
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ctx->superscalar[1].v[1] = b2;
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ctx->superscalar[2].v[1] = c2;
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ctx->superscalar[3].v[1] = d2;
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ctx->superscalar[0].v[2] = a3;
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ctx->superscalar[1].v[2] = b3;
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ctx->superscalar[2].v[2] = c3;
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ctx->superscalar[3].v[2] = d3;
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ctx->superscalar[0].v[3] = a4;
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ctx->superscalar[1].v[3] = b4;
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ctx->superscalar[2].v[3] = c4;
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ctx->superscalar[3].v[3] = d4;
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}
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ZFS_NO_SANITIZE_UNDEFINED
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static void
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fletcher_4_superscalar4_byteswap(fletcher_4_ctx_t *ctx,
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const void *buf, uint64_t size)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = ip + (size / sizeof (uint32_t));
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uint64_t a, b, c, d;
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uint64_t a2, b2, c2, d2;
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uint64_t a3, b3, c3, d3;
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uint64_t a4, b4, c4, d4;
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a = ctx->superscalar[0].v[0];
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b = ctx->superscalar[1].v[0];
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c = ctx->superscalar[2].v[0];
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d = ctx->superscalar[3].v[0];
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a2 = ctx->superscalar[0].v[1];
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b2 = ctx->superscalar[1].v[1];
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c2 = ctx->superscalar[2].v[1];
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d2 = ctx->superscalar[3].v[1];
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a3 = ctx->superscalar[0].v[2];
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b3 = ctx->superscalar[1].v[2];
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c3 = ctx->superscalar[2].v[2];
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d3 = ctx->superscalar[3].v[2];
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a4 = ctx->superscalar[0].v[3];
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b4 = ctx->superscalar[1].v[3];
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c4 = ctx->superscalar[2].v[3];
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d4 = ctx->superscalar[3].v[3];
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do {
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a += BSWAP_32(ip[0]);
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a2 += BSWAP_32(ip[1]);
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a3 += BSWAP_32(ip[2]);
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a4 += BSWAP_32(ip[3]);
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b += a;
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b2 += a2;
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b3 += a3;
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b4 += a4;
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c += b;
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c2 += b2;
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c3 += b3;
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c4 += b4;
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d += c;
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d2 += c2;
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d3 += c3;
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d4 += c4;
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} while ((ip += 4) < ipend);
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ctx->superscalar[0].v[0] = a;
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ctx->superscalar[1].v[0] = b;
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ctx->superscalar[2].v[0] = c;
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ctx->superscalar[3].v[0] = d;
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ctx->superscalar[0].v[1] = a2;
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ctx->superscalar[1].v[1] = b2;
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ctx->superscalar[2].v[1] = c2;
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ctx->superscalar[3].v[1] = d2;
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ctx->superscalar[0].v[2] = a3;
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ctx->superscalar[1].v[2] = b3;
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ctx->superscalar[2].v[2] = c3;
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ctx->superscalar[3].v[2] = d3;
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ctx->superscalar[0].v[3] = a4;
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ctx->superscalar[1].v[3] = b4;
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ctx->superscalar[2].v[3] = c4;
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ctx->superscalar[3].v[3] = d4;
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}
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static boolean_t fletcher_4_superscalar4_valid(void)
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{
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return (B_TRUE);
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}
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const fletcher_4_ops_t fletcher_4_superscalar4_ops = {
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.init_native = fletcher_4_superscalar4_init,
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.compute_native = fletcher_4_superscalar4_native,
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.fini_native = fletcher_4_superscalar4_fini,
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.init_byteswap = fletcher_4_superscalar4_init,
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.compute_byteswap = fletcher_4_superscalar4_byteswap,
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.fini_byteswap = fletcher_4_superscalar4_fini,
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.valid = fletcher_4_superscalar4_valid,
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.name = "superscalar4"
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};
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