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703371d8c7
The problem is described in commit aeeb4e0c0a.
However, instead of disabling the binding to CPU altogether we just keep the
last CPU index across calls to taskq_create() and thus achieve even
distribution of the taskq threads across all available CPUs.
The implementation based on assumption that task queues initialization
performed in serial manner.
Signed-off-by: Andrey Vesnovaty <andrey.vesnovaty@gmail.com>
Signed-off-by: Andrey Vesnovaty <andreyv@infinidat.com>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #336
139 lines
1.9 KiB
Groff
139 lines
1.9 KiB
Groff
'\" te
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.\"
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.\" Copyright 2013 Turbo Fredriksson <turbo@bayour.com>. All rights reserved.
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.\"
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.TH SPL-MODULE-PARAMETERS 5 "Nov 18, 2013"
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.SH NAME
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spl\-module\-parameters \- SPL module parameters
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.SH DESCRIPTION
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.sp
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.LP
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Description of the different parameters to the SPL module.
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.SS "Module parameters"
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.sp
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.LP
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.sp
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.ne 2
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.na
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\fBspl_debug_subsys\fR (ulong)
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.ad
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.RS 12n
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Subsystem debugging level mask.
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.sp
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Default value: \fB~0\fR.
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.RE
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.sp
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.ne 2
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.na
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\fBspl_debug_mask\fR (ulong)
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.ad
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.RS 12n
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Debugging level mask.
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.sp
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Default value: \fB8 | 10 | 4 | 20\fR (SD_ERROR | SD_EMERG | SD_WARNING | SD_CONSOLE).
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.RE
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.sp
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.ne 2
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.na
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\fBspl_debug_printk\fR (ulong)
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.ad
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.RS 12n
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Console printk level mask.
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.sp
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Default value: \fB8 | 10 | 4 | 20\fR (SD_ERROR | SD_EMERG | SD_WARNING | SD_CONSOLE).
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.RE
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.sp
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.ne 2
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.na
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\fBspl_debug_mb\fR (int)
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.ad
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.RS 12n
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Total debug buffer size.
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.sp
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Default value: \fB-1\fR.
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.RE
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.sp
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.ne 2
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.na
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\fBspl_debug_panic_on_bug\fR (int)
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.ad
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.RS 12n
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Panic on BUG
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.sp
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Use \fB1\fR for yes and \fB0\fR for no (default).
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.RE
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.sp
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.ne 2
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.na
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\fBspl_kmem_cache_expire\fR (uint)
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.ad
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.RS 12n
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By age (0x1) or low memory (0x2)
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.sp
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Default value: \fB0\fR.
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.RE
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.sp
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.ne 2
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.na
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\fBspl_hostid\fR (ulong)
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.ad
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.RS 12n
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The system hostid.
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.sp
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Default value: \fB0xFFFFFFFF\fR (an invalid hostid!)
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.RE
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.sp
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.ne 2
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.na
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\fBspl_hostid_path\fR (charp)
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.ad
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.RS 12n
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The system hostid file
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.sp
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Default value: \fB/etc/hostid\fR.
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.RE
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.sp
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.ne 2
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.na
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\fBmutex_spin_max\fR (int)
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.ad
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.RS 12n
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Spin a maximum of N times to acquire lock
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.sp
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.ne 2
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.na
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\fBPossible values:\fR
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.sp
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.RS 12n
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\fB0\fR Never spin when trying to acquire lock
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.sp
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\fB-1\fR Spin until acquired or holder yields without dropping lock
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.sp
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\fB1-MAX_INT\fR Spin for N attempts before sleeping for lock
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.RE
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.sp
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.ne -4
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Default value: \fB0\fR.
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.RE
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.sp
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.ne 2
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.na
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\fBspl_taskq_thread_bind\fR (int)
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.ad
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.RS 12n
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Bind taskq thread to CPU
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.sp
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Default value: \fB0\fR.
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.RE
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