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62c034f6d4
Restore the SIMD optimization for 4.19.38 LTS, 4.14.120 LTS, and 5.0 and newer kernels. This commit squashes the following commits from master in to a single commit which can be applied to 0.8.2.10fa2545- Linux 4.14, 4.19, 5.0+ compat: SIMD save/restoreb88ca2ac- Enable SIMD for encryption095b5412- Fix CONFIG_X86_DEBUG_FPU build failuree5db3134- Linux 5.0 compat: SIMD compatibility Reviewed-by: Fabian Grünbichler <f.gruenbichler@proxmox.com> Reviewed-by: Tony Hutter <hutter2@llnl.gov> Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov> TEST_ZIMPORT_SKIP="yes"
216 lines
7.6 KiB
C
216 lines
7.6 KiB
C
/*
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* Implement fast Fletcher4 with NEON instructions. (aarch64)
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*
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* Use the 128-bit NEON SIMD instructions and registers to compute
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* Fletcher4 in two incremental 64-bit parallel accumulator streams,
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* and then combine the streams to form the final four checksum words.
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* This implementation is a derivative of the AVX SIMD implementation by
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* James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c).
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*
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* Copyright (C) 2016 Romain Dolbeau.
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*
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* Authors:
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* Romain Dolbeau <romain.dolbeau@atos.net>
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(__aarch64__)
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#include <linux/simd_aarch64.h>
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#include <sys/spa_checksum.h>
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#include <sys/strings.h>
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#include <zfs_fletcher.h>
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static void
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fletcher_4_aarch64_neon_init(fletcher_4_ctx_t *ctx)
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{
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bzero(ctx->aarch64_neon, 4 * sizeof (zfs_fletcher_aarch64_neon_t));
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}
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static void
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fletcher_4_aarch64_neon_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp)
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{
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uint64_t A, B, C, D;
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A = ctx->aarch64_neon[0].v[0] + ctx->aarch64_neon[0].v[1];
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B = 2 * ctx->aarch64_neon[1].v[0] + 2 * ctx->aarch64_neon[1].v[1] -
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ctx->aarch64_neon[0].v[1];
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C = 4 * ctx->aarch64_neon[2].v[0] - ctx->aarch64_neon[1].v[0] +
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4 * ctx->aarch64_neon[2].v[1] - 3 * ctx->aarch64_neon[1].v[1];
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D = 8 * ctx->aarch64_neon[3].v[0] - 4 * ctx->aarch64_neon[2].v[0] +
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8 * ctx->aarch64_neon[3].v[1] - 8 * ctx->aarch64_neon[2].v[1] +
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ctx->aarch64_neon[1].v[1];
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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#define NEON_INIT_LOOP() \
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asm("eor %[ZERO].16b,%[ZERO].16b,%[ZERO].16b\n" \
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"ld1 { %[ACC0].4s }, %[CTX0]\n" \
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"ld1 { %[ACC1].4s }, %[CTX1]\n" \
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"ld1 { %[ACC2].4s }, %[CTX2]\n" \
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"ld1 { %[ACC3].4s }, %[CTX3]\n" \
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: [ZERO] "=w" (ZERO), \
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[ACC0] "=w" (ACC0), [ACC1] "=w" (ACC1), \
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[ACC2] "=w" (ACC2), [ACC3] "=w" (ACC3) \
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: [CTX0] "Q" (ctx->aarch64_neon[0]), \
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[CTX1] "Q" (ctx->aarch64_neon[1]), \
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[CTX2] "Q" (ctx->aarch64_neon[2]), \
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[CTX3] "Q" (ctx->aarch64_neon[3]))
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#define NEON_DO_REVERSE "rev32 %[SRC].16b, %[SRC].16b\n"
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#define NEON_DONT_REVERSE ""
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#define NEON_MAIN_LOOP(REVERSE) \
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asm("ld1 { %[SRC].4s }, %[IP]\n" \
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REVERSE \
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"zip1 %[TMP1].4s, %[SRC].4s, %[ZERO].4s\n" \
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"zip2 %[TMP2].4s, %[SRC].4s, %[ZERO].4s\n" \
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"add %[ACC0].2d, %[ACC0].2d, %[TMP1].2d\n" \
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"add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n" \
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"add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n" \
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"add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n" \
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"add %[ACC0].2d, %[ACC0].2d, %[TMP2].2d\n" \
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"add %[ACC1].2d, %[ACC1].2d, %[ACC0].2d\n" \
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"add %[ACC2].2d, %[ACC2].2d, %[ACC1].2d\n" \
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"add %[ACC3].2d, %[ACC3].2d, %[ACC2].2d\n" \
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: [SRC] "=&w" (SRC), \
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[TMP1] "=&w" (TMP1), [TMP2] "=&w" (TMP2), \
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[ACC0] "+w" (ACC0), [ACC1] "+w" (ACC1), \
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[ACC2] "+w" (ACC2), [ACC3] "+w" (ACC3) \
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: [ZERO] "w" (ZERO), [IP] "Q" (*ip))
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#define NEON_FINI_LOOP() \
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asm("st1 { %[ACC0].4s },%[DST0]\n" \
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"st1 { %[ACC1].4s },%[DST1]\n" \
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"st1 { %[ACC2].4s },%[DST2]\n" \
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"st1 { %[ACC3].4s },%[DST3]\n" \
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: [DST0] "=Q" (ctx->aarch64_neon[0]), \
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[DST1] "=Q" (ctx->aarch64_neon[1]), \
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[DST2] "=Q" (ctx->aarch64_neon[2]), \
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[DST3] "=Q" (ctx->aarch64_neon[3]) \
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: [ACC0] "w" (ACC0), [ACC1] "w" (ACC1), \
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[ACC2] "w" (ACC2), [ACC3] "w" (ACC3))
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static void
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fletcher_4_aarch64_neon_native(fletcher_4_ctx_t *ctx,
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const void *buf, uint64_t size)
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{
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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#if defined(_KERNEL)
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register unsigned char ZERO asm("v0") __attribute__((vector_size(16)));
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register unsigned char ACC0 asm("v1") __attribute__((vector_size(16)));
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register unsigned char ACC1 asm("v2") __attribute__((vector_size(16)));
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register unsigned char ACC2 asm("v3") __attribute__((vector_size(16)));
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register unsigned char ACC3 asm("v4") __attribute__((vector_size(16)));
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register unsigned char TMP1 asm("v5") __attribute__((vector_size(16)));
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register unsigned char TMP2 asm("v6") __attribute__((vector_size(16)));
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register unsigned char SRC asm("v7") __attribute__((vector_size(16)));
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#else
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unsigned char ZERO __attribute__((vector_size(16)));
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unsigned char ACC0 __attribute__((vector_size(16)));
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unsigned char ACC1 __attribute__((vector_size(16)));
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unsigned char ACC2 __attribute__((vector_size(16)));
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unsigned char ACC3 __attribute__((vector_size(16)));
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unsigned char TMP1 __attribute__((vector_size(16)));
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unsigned char TMP2 __attribute__((vector_size(16)));
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unsigned char SRC __attribute__((vector_size(16)));
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#endif
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kfpu_begin();
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NEON_INIT_LOOP();
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for (; ip < ipend; ip += 2) {
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NEON_MAIN_LOOP(NEON_DONT_REVERSE);
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}
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NEON_FINI_LOOP();
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kfpu_end();
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}
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static void
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fletcher_4_aarch64_neon_byteswap(fletcher_4_ctx_t *ctx,
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const void *buf, uint64_t size)
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{
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const uint64_t *ip = buf;
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const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
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#if defined(_KERNEL)
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register unsigned char ZERO asm("v0") __attribute__((vector_size(16)));
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register unsigned char ACC0 asm("v1") __attribute__((vector_size(16)));
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register unsigned char ACC1 asm("v2") __attribute__((vector_size(16)));
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register unsigned char ACC2 asm("v3") __attribute__((vector_size(16)));
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register unsigned char ACC3 asm("v4") __attribute__((vector_size(16)));
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register unsigned char TMP1 asm("v5") __attribute__((vector_size(16)));
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register unsigned char TMP2 asm("v6") __attribute__((vector_size(16)));
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register unsigned char SRC asm("v7") __attribute__((vector_size(16)));
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#else
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unsigned char ZERO __attribute__((vector_size(16)));
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unsigned char ACC0 __attribute__((vector_size(16)));
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unsigned char ACC1 __attribute__((vector_size(16)));
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unsigned char ACC2 __attribute__((vector_size(16)));
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unsigned char ACC3 __attribute__((vector_size(16)));
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unsigned char TMP1 __attribute__((vector_size(16)));
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unsigned char TMP2 __attribute__((vector_size(16)));
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unsigned char SRC __attribute__((vector_size(16)));
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#endif
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kfpu_begin();
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NEON_INIT_LOOP();
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for (; ip < ipend; ip += 2) {
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NEON_MAIN_LOOP(NEON_DO_REVERSE);
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}
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NEON_FINI_LOOP();
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kfpu_end();
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}
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static boolean_t fletcher_4_aarch64_neon_valid(void)
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{
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return (kfpu_allowed());
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}
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const fletcher_4_ops_t fletcher_4_aarch64_neon_ops = {
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.init_native = fletcher_4_aarch64_neon_init,
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.compute_native = fletcher_4_aarch64_neon_native,
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.fini_native = fletcher_4_aarch64_neon_fini,
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.init_byteswap = fletcher_4_aarch64_neon_init,
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.compute_byteswap = fletcher_4_aarch64_neon_byteswap,
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.fini_byteswap = fletcher_4_aarch64_neon_fini,
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.valid = fletcher_4_aarch64_neon_valid,
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.name = "aarch64_neon"
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};
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#endif /* defined(__aarch64__) */
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