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https://git.proxmox.com/git/mirror_zfs.git
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e5db313494
Restore the SIMD optimization for 4.19.38 LTS, 4.14.120 LTS,
and 5.0 and newer kernels. This is accomplished by leveraging
the fact that by definition dedicated kernel threads never need
to concern themselves with saving and restoring the user FPU state.
Therefore, they may use the FPU as long as we can guarantee user
tasks always restore their FPU state before context switching back
to user space.
For the 5.0 and 5.1 kernels disabling preemption and local
interrupts is sufficient to allow the FPU to be used. All non-kernel
threads will restore the preserved user FPU state.
For 5.2 and latter kernels the user FPU state restoration will be
skipped if the kernel determines the registers have not changed.
Therefore, for these kernels we need to perform the additional
step of saving and restoring the FPU registers. Invalidating the
per-cpu global tracking the FPU state would force a restore but
that functionality is private to the core x86 FPU implementation
and unavailable.
In practice, restricting SIMD to kernel threads is not a major
restriction for ZFS. The vast majority of SIMD operations are
already performed by the IO pipeline. The remaining cases are
relatively infrequent and can be handled by the generic code
without significant impact. The two most noteworthy cases are:
1) Decrypting the wrapping key for an encrypted dataset,
i.e. `zfs load-key`. All other encryption and decryption
operations will use the SIMD optimized implementations.
2) Generating the payload checksums for a `zfs send` stream.
In order to avoid making any changes to the higher layers of ZFS
all of the `*_get_ops()` functions were updated to take in to
consideration the calling context. This allows for the fastest
implementation to be used as appropriate (see kfpu_allowed()).
The only other notable instance of SIMD operations being used
outside a kernel thread was at module load time. This code
was moved in to a taskq in order to accommodate the new kernel
thread restriction.
Finally, a few other modifications were made in order to further
harden this code and facilitate testing. They include updating
each implementations operations structure to be declared as a
constant. And allowing "cycle" to be set when selecting the
preferred ops in the kernel as well as user space.
Reviewed-by: Tony Hutter <hutter2@llnl.gov>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #8754
Closes #8793
Closes #8965
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Nešković. All rights reserved.
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*/
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#include <sys/isa_defs.h>
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#if defined(__x86_64) && defined(HAVE_AVX2)
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#include <sys/types.h>
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#include <linux/simd_x86.h>
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#define __asm __asm__ __volatile__
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#define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
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#define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
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#define VR0_(REG, ...) "ymm"#REG
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#define VR1_(_1, REG, ...) "ymm"#REG
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#define VR2_(_1, _2, REG, ...) "ymm"#REG
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#define VR3_(_1, _2, _3, REG, ...) "ymm"#REG
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#define VR4_(_1, _2, _3, _4, REG, ...) "ymm"#REG
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#define VR5_(_1, _2, _3, _4, _5, REG, ...) "ymm"#REG
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#define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "ymm"#REG
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#define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "ymm"#REG
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#define VR0(r...) VR0_(r)
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#define VR1(r...) VR1_(r)
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#define VR2(r...) VR2_(r, 1)
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#define VR3(r...) VR3_(r, 1, 2)
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#define VR4(r...) VR4_(r, 1, 2)
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#define VR5(r...) VR5_(r, 1, 2, 3)
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#define VR6(r...) VR6_(r, 1, 2, 3, 4)
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#define VR7(r...) VR7_(r, 1, 2, 3, 4, 5)
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#define R_01(REG1, REG2, ...) REG1, REG2
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#define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3
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#define R_23(REG...) _R_23(REG, 1, 2, 3)
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#define ZFS_ASM_BUG() ASSERT(0)
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extern const uint8_t gf_clmul_mod_lt[4*256][16];
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#define ELEM_SIZE 32
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typedef struct v {
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uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
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} v_t;
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#define XOR_ACC(src, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
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"vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
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"vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n" \
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"vpxor 0x60(%[SRC]), %%" VR3(r)", %%" VR3(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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case 2: \
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__asm( \
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"vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n" \
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"vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define XOR(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 8: \
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__asm( \
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"vpxor %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n" \
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"vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n" \
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"vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n" \
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"vpxor %" VR3(r) ", %" VR7(r)", %" VR7(r)); \
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break; \
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case 4: \
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__asm( \
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"vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n" \
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"vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define ZERO(r...) XOR(r, r)
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#define COPY(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 8: \
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__asm( \
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"vmovdqa %" VR0(r) ", %" VR4(r) "\n" \
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"vmovdqa %" VR1(r) ", %" VR5(r) "\n" \
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"vmovdqa %" VR2(r) ", %" VR6(r) "\n" \
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"vmovdqa %" VR3(r) ", %" VR7(r)); \
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break; \
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case 4: \
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__asm( \
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"vmovdqa %" VR0(r) ", %" VR2(r) "\n" \
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"vmovdqa %" VR1(r) ", %" VR3(r)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define LOAD(src, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
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"vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
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"vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n" \
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"vmovdqa 0x60(%[SRC]), %%" VR3(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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case 2: \
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__asm( \
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"vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n" \
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"vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n" \
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: : [SRC] "r" (src)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define STORE(dst, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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__asm( \
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"vmovdqa %%" VR0(r) ", 0x00(%[DST])\n" \
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"vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
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"vmovdqa %%" VR2(r) ", 0x40(%[DST])\n" \
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"vmovdqa %%" VR3(r) ", 0x60(%[DST])\n" \
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: : [DST] "r" (dst)); \
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break; \
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case 2: \
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__asm( \
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"vmovdqa %%" VR0(r) ", 0x00(%[DST])\n" \
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"vmovdqa %%" VR1(r) ", 0x20(%[DST])\n" \
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: : [DST] "r" (dst)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define FLUSH() \
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{ \
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__asm("vzeroupper"); \
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}
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#define MUL2_SETUP() \
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{ \
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__asm("vmovq %0, %%xmm14" :: "r"(0x1d1d1d1d1d1d1d1d)); \
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__asm("vpbroadcastq %xmm14, %ymm14"); \
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__asm("vpxor %ymm15, %ymm15 ,%ymm15"); \
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}
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#define _MUL2(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 2: \
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__asm( \
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"vpcmpgtb %" VR0(r)", %ymm15, %ymm12\n" \
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"vpcmpgtb %" VR1(r)", %ymm15, %ymm13\n" \
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"vpaddb %" VR0(r)", %" VR0(r)", %" VR0(r) "\n" \
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"vpaddb %" VR1(r)", %" VR1(r)", %" VR1(r) "\n" \
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"vpand %ymm14, %ymm12, %ymm12\n" \
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"vpand %ymm14, %ymm13, %ymm13\n" \
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"vpxor %ymm12, %" VR0(r)", %" VR0(r) "\n" \
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"vpxor %ymm13, %" VR1(r)", %" VR1(r)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define MUL2(r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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_MUL2(R_01(r)); \
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_MUL2(R_23(r)); \
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break; \
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case 2: \
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_MUL2(r); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define MUL4(r...) \
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{ \
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MUL2(r); \
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MUL2(r); \
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}
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#define _0f "ymm15"
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#define _as "ymm14"
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#define _bs "ymm13"
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#define _ltmod "ymm12"
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#define _ltmul "ymm11"
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#define _ta "ymm10"
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#define _tb "ymm15"
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static const uint8_t __attribute__((aligned(32))) _mul_mask = 0x0F;
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#define _MULx2(c, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 2: \
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__asm( \
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"vpbroadcastb (%[mask]), %%" _0f "\n" \
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/* upper bits */ \
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"vbroadcasti128 0x00(%[lt]), %%" _ltmod "\n" \
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"vbroadcasti128 0x10(%[lt]), %%" _ltmul "\n" \
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\
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"vpsraw $0x4, %%" VR0(r) ", %%"_as "\n" \
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"vpsraw $0x4, %%" VR1(r) ", %%"_bs "\n" \
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"vpand %%" _0f ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpand %%" _0f ", %%" VR1(r) ", %%" VR1(r) "\n" \
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"vpand %%" _0f ", %%" _as ", %%" _as "\n" \
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"vpand %%" _0f ", %%" _bs ", %%" _bs "\n" \
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\
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"vpshufb %%" _as ", %%" _ltmod ", %%" _ta "\n" \
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"vpshufb %%" _bs ", %%" _ltmod ", %%" _tb "\n" \
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"vpshufb %%" _as ", %%" _ltmul ", %%" _as "\n" \
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"vpshufb %%" _bs ", %%" _ltmul ", %%" _bs "\n" \
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/* lower bits */ \
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"vbroadcasti128 0x20(%[lt]), %%" _ltmod "\n" \
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"vbroadcasti128 0x30(%[lt]), %%" _ltmul "\n" \
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\
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"vpxor %%" _ta ", %%" _as ", %%" _as "\n" \
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"vpxor %%" _tb ", %%" _bs ", %%" _bs "\n" \
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\
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"vpshufb %%" VR0(r) ", %%" _ltmod ", %%" _ta "\n" \
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"vpshufb %%" VR1(r) ", %%" _ltmod ", %%" _tb "\n" \
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"vpshufb %%" VR0(r) ", %%" _ltmul ", %%" VR0(r) "\n"\
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"vpshufb %%" VR1(r) ", %%" _ltmul ", %%" VR1(r) "\n"\
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\
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"vpxor %%" _ta ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpxor %%" _as ", %%" VR0(r) ", %%" VR0(r) "\n" \
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"vpxor %%" _tb ", %%" VR1(r) ", %%" VR1(r) "\n" \
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"vpxor %%" _bs ", %%" VR1(r) ", %%" VR1(r) "\n" \
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: : [mask] "r" (&_mul_mask), \
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[lt] "r" (gf_clmul_mod_lt[4*(c)])); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define MUL(c, r...) \
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{ \
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switch (REG_CNT(r)) { \
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case 4: \
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_MULx2(c, R_01(r)); \
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_MULx2(c, R_23(r)); \
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break; \
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case 2: \
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_MULx2(c, R_01(r)); \
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break; \
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default: \
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ZFS_ASM_BUG(); \
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} \
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}
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#define raidz_math_begin() kfpu_begin()
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#define raidz_math_end() \
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{ \
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FLUSH(); \
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kfpu_end(); \
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}
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#define SYN_STRIDE 4
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#define ZERO_STRIDE 4
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#define ZERO_DEFINE() {}
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#define ZERO_D 0, 1, 2, 3
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#define COPY_STRIDE 4
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#define COPY_DEFINE() {}
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#define COPY_D 0, 1, 2, 3
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#define ADD_STRIDE 4
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#define ADD_DEFINE() {}
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#define ADD_D 0, 1, 2, 3
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#define MUL_STRIDE 4
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#define MUL_DEFINE() {}
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#define MUL_D 0, 1, 2, 3
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#define GEN_P_STRIDE 4
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#define GEN_P_DEFINE() {}
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#define GEN_P_P 0, 1, 2, 3
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#define GEN_PQ_STRIDE 4
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#define GEN_PQ_DEFINE() {}
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#define GEN_PQ_D 0, 1, 2, 3
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#define GEN_PQ_C 4, 5, 6, 7
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#define GEN_PQR_STRIDE 4
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#define GEN_PQR_DEFINE() {}
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#define GEN_PQR_D 0, 1, 2, 3
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#define GEN_PQR_C 4, 5, 6, 7
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#define SYN_Q_DEFINE() {}
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#define SYN_Q_D 0, 1, 2, 3
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#define SYN_Q_X 4, 5, 6, 7
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#define SYN_R_DEFINE() {}
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#define SYN_R_D 0, 1, 2, 3
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#define SYN_R_X 4, 5, 6, 7
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#define SYN_PQ_DEFINE() {}
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#define SYN_PQ_D 0, 1, 2, 3
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#define SYN_PQ_X 4, 5, 6, 7
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#define REC_PQ_STRIDE 2
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#define REC_PQ_DEFINE() {}
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#define REC_PQ_X 0, 1
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#define REC_PQ_Y 2, 3
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#define REC_PQ_T 4, 5
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#define SYN_PR_DEFINE() {}
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#define SYN_PR_D 0, 1, 2, 3
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#define SYN_PR_X 4, 5, 6, 7
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#define REC_PR_STRIDE 2
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#define REC_PR_DEFINE() {}
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#define REC_PR_X 0, 1
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#define REC_PR_Y 2, 3
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#define REC_PR_T 4, 5
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#define SYN_QR_DEFINE() {}
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#define SYN_QR_D 0, 1, 2, 3
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#define SYN_QR_X 4, 5, 6, 7
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#define REC_QR_STRIDE 2
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#define REC_QR_DEFINE() {}
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#define REC_QR_X 0, 1
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#define REC_QR_Y 2, 3
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#define REC_QR_T 4, 5
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#define SYN_PQR_DEFINE() {}
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#define SYN_PQR_D 0, 1, 2, 3
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#define SYN_PQR_X 4, 5, 6, 7
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#define REC_PQR_STRIDE 2
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#define REC_PQR_DEFINE() {}
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#define REC_PQR_X 0, 1
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#define REC_PQR_Y 2, 3
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#define REC_PQR_Z 4, 5
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#define REC_PQR_XS 6, 7
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#define REC_PQR_YS 8, 9
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#include <sys/vdev_raidz_impl.h>
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#include "vdev_raidz_math_impl.h"
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DEFINE_GEN_METHODS(avx2);
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DEFINE_REC_METHODS(avx2);
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static boolean_t
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raidz_will_avx2_work(void)
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{
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return (kfpu_allowed() && zfs_avx_available() && zfs_avx2_available());
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}
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const raidz_impl_ops_t vdev_raidz_avx2_impl = {
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.init = NULL,
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.fini = NULL,
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.gen = RAIDZ_GEN_METHODS(avx2),
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.rec = RAIDZ_REC_METHODS(avx2),
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.is_supported = &raidz_will_avx2_work,
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.name = "avx2"
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};
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#endif /* defined(__x86_64) && defined(HAVE_AVX2) */
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