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Backport AVX2 AES-GCM implementation from BoringSSL

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This uses the AVX2 versions of the AESENC and PCLMULQDQ instructions; on
Zen 3 this provides an up to 80% performance improvement.

Original source:
https://github.com/google/boringssl/blob/d5440dd2c2c500ac2d3bba4afec47a054b4d99ae/gen/bcm/aes-gcm-avx2-x86_64-linux.S

See the original BoringSSL commit at
https://github.com/google/boringssl/commit/3b6e1be4391d96e81cee022f77f7bab85d51cf4e.

Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed-by: Rob Norris <robn@despairlabs.com>
Reviewed-by: Tony Hutter <hutter2@llnl.gov>
Reviewed-by: Attila Fülöp <attila@fueloep.org>
Signed-off-by: Joel Low <joel@joelsplace.sg>
Closes #17058
This commit is contained in:
Joel Low
2025-02-15 11:37:33 +08:00
committed by Brian Behlendorf
parent 885d929cf8
commit bb9225ea86
15 changed files with 3574 additions and 82 deletions
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lib/libspl/include/sys/simd.h
+27 -1
View File
@@ -102,7 +102,9 @@ typedef enum cpuid_inst_sets {
AES,
PCLMULQDQ,
MOVBE,
SHA_NI
SHA_NI,
VAES,
VPCLMULQDQ
} cpuid_inst_sets_t;
/*
@@ -127,6 +129,8 @@ typedef struct cpuid_feature_desc {
#define _AES_BIT (1U << 25)
#define _PCLMULQDQ_BIT (1U << 1)
#define _MOVBE_BIT (1U << 22)
#define _VAES_BIT (1U << 9)
#define _VPCLMULQDQ_BIT (1U << 10)
#define _SHA_NI_BIT (1U << 29)
/*
@@ -157,6 +161,8 @@ static const cpuid_feature_desc_t cpuid_features[] = {
[PCLMULQDQ] = {1U, 0U, _PCLMULQDQ_BIT, ECX },
[MOVBE] = {1U, 0U, _MOVBE_BIT, ECX },
[SHA_NI] = {7U, 0U, _SHA_NI_BIT, EBX },
[VAES] = {7U, 0U, _VAES_BIT, ECX },
[VPCLMULQDQ] = {7U, 0U, _VPCLMULQDQ_BIT, ECX },
};
/*
@@ -231,6 +237,8 @@ CPUID_FEATURE_CHECK(aes, AES);
CPUID_FEATURE_CHECK(pclmulqdq, PCLMULQDQ);
CPUID_FEATURE_CHECK(movbe, MOVBE);
CPUID_FEATURE_CHECK(shani, SHA_NI);
CPUID_FEATURE_CHECK(vaes, VAES);
CPUID_FEATURE_CHECK(vpclmulqdq, VPCLMULQDQ);
/*
* Detect register set support
@@ -381,6 +389,24 @@ zfs_shani_available(void)
return (__cpuid_has_shani());
}
/*
* Check if VAES instruction is available
*/
static inline boolean_t
zfs_vaes_available(void)
{
return (__cpuid_has_vaes());
}
/*
* Check if VPCLMULQDQ instruction is available
*/
static inline boolean_t
zfs_vpclmulqdq_available(void)
{
return (__cpuid_has_vpclmulqdq());
}
/*
* AVX-512 family of instruction sets:
*