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Fix ARM 64-bit division
Correctly implementating 64-bit division for ARM requires more than just providing the __aeabi_uldivmod() and __aeabi_ldivmod() symbols. They are need to be implemented is such a way that the quotient and remainder and left in specific registers after the division operation completes. This change updates the wrapper functions to accomplish this according to the official ARM Run-time ABI. Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov> Closes zfsonlinux/zfs#706
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@ -214,22 +214,57 @@ EXPORT_SYMBOL(__umoddi3);
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#if defined(__arm) || defined(__arm__)
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/*
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* Implementation of 64-bit unsigned division for 32-bit arm machines.
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* Implementation of 64-bit (un)signed division for 32-bit arm machines.
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*
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* Run-time ABI for the ARM Architecture (page 20). A pair of (unsigned)
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* long longs is returned in {{r0, r1}, {r2,r3}}, the quotient in {r0, r1},
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* and the remainder in {r2, r3}. The return type is specifically left
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* set to 'void' to ensure the compiler does not overwrite these registers
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* during the return. All results are in registers as per ABI
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*/
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uint64_t
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void
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__aeabi_uldivmod(uint64_t u, uint64_t v)
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{
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return __udivdi3(u, v);
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uint64_t res;
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uint64_t mod;
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res = __udivdi3(u, v);
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mod = __umoddi3(u, v);
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{
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register uint32_t r0 asm("r0") = (res & 0xFFFFFFFF);
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register uint32_t r1 asm("r1") = (res >> 32);
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register uint32_t r2 asm("r2") = (mod & 0xFFFFFFFF);
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register uint32_t r3 asm("r3") = (mod >> 32);
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asm volatile(""
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: "+r"(r0), "+r"(r1), "+r"(r2),"+r"(r3) /* output */
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: "r"(r0), "r"(r1), "r"(r2), "r"(r3)); /* input */
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return; /* r0; */
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}
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}
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EXPORT_SYMBOL(__aeabi_uldivmod);
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/*
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* Implementation of 64-bit signed division for 32-bit arm machines.
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*/
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int64_t
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void
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__aeabi_ldivmod(int64_t u, int64_t v)
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{
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return __divdi3(u, v);
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int64_t res;
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uint64_t mod;
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res = __divdi3(u, v);
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mod = __umoddi3(u, v);
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{
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register uint32_t r0 asm("r0") = (res & 0xFFFFFFFF);
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register uint32_t r1 asm("r1") = (res >> 32);
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register uint32_t r2 asm("r2") = (mod & 0xFFFFFFFF);
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register uint32_t r3 asm("r3") = (mod >> 32);
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asm volatile(""
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: "+r"(r0), "+r"(r1), "+r"(r2),"+r"(r3) /* output */
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: "r"(r0), "r"(r1), "r"(r2), "r"(r3)); /* input */
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return; /* r0; */
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}
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}
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EXPORT_SYMBOL(__aeabi_ldivmod);
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#endif /* __arm || __arm__ */
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