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Fletcher4 implementation using avx512f instruction set
Algorithm runs 8 parallel sums, consuming 8x uint32_t elements per loop iteration. Size alignment of main fletcher4 methods is adjusted accordingly. New implementation is called 'avx512f'. Note: byteswap method can be implemented more efficiently when avx512bw hardware becomes available. Currently, it is ~ 2x slower than native method. Table shows result of full (native) fletcher4 calculation for different buffer size: fletcher4 4KB 16KB 64KB 128KB 256KB 1MB 16MB -------------------------------------------------------------------- [scalar] 1213 1228 1231 1231 1225 1200 1160 [sse2] 2374 2442 2459 2456 2462 2250 2220 [avx2] 4288 4753 4871 4893 4900 4050 3882 [avx512f] 5975 8445 9196 9221 9262 6307 5620 Signed-off-by: Gvozden Neskovic <neskovic@gmail.com> Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov> Issue #4952
This commit is contained in:
Gvozden Neskovic
Brian Behlendorf
parent
32ffaa3de5
commit
70b258fc96
@ -73,6 +73,10 @@ extern const fletcher_4_ops_t fletcher_4_ssse3_ops;
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extern const fletcher_4_ops_t fletcher_4_avx2_ops;
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#endif
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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extern const fletcher_4_ops_t fletcher_4_avx512f_ops;
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#endif
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#ifdef __cplusplus
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}
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#endif
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@ -24,6 +24,7 @@ KERNEL_C = \
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zfs_fletcher.c \
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zfs_fletcher_intel.c \
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zfs_fletcher_sse.c \
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zfs_fletcher_avx512.c \
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zfs_namecheck.c \
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zfs_prop.c \
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zfs_uio.c \
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@ -883,14 +883,14 @@ Default value: \fB67,108,864\fR.
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Select a fletcher 4 implementation.
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.sp
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Supported selectors are: \fBfastest\fR, \fBscalar\fR, \fBsse2\fR, \fBssse3\fR,
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and \fBavx2\fR. All of the selectors except \fBfastest\fR and \fBscalar\fR
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require instruction set extensions to be available and will only appear if ZFS
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detects that they are present at runtime. If multiple implementations of
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fletcher 4 are available, the \fBfastest\fR will be chosen using a micro
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benchmark. Selecting \fBscalar\fR results in the original CPU based calculation
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being used. Selecting any option other than \fBfastest\fR and \fBscalar\fR
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results in vector instructions from the respective CPU instruction set being
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used.
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\fBavx2\fR, and \fBavx512f\fR.
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All of the selectors except \fBfastest\fR and \fBscalar\fR require instruction
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set extensions to be available and will only appear if ZFS detects that they are
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present at runtime. If multiple implementations of fletcher 4 are available,
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the \fBfastest\fR will be chosen using a micro benchmark. Selecting \fBscalar\fR
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results in the original, CPU based calculation, being used. Selecting any option
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other than \fBfastest\fR and \fBscalar\fR results in vector instructions from
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the respective CPU instruction set being used.
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.sp
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Default value: \fBfastest\fR.
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.RE
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@ -18,3 +18,4 @@ $(MODULE)-objs += zpool_prop.o
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$(MODULE)-$(CONFIG_X86) += zfs_fletcher_intel.o
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$(MODULE)-$(CONFIG_X86) += zfs_fletcher_sse.o
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$(MODULE)-$(CONFIG_X86) += zfs_fletcher_avx512.o
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@ -158,6 +158,9 @@ static const fletcher_4_ops_t *fletcher_4_algos[] = {
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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&fletcher_4_avx2_ops,
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#endif
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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&fletcher_4_avx512f_ops,
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#endif
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};
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static enum fletcher_selector {
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@ -171,6 +174,9 @@ static enum fletcher_selector {
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#endif
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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FLETCHER_AVX2,
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#endif
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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FLETCHER_AVX512F,
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#endif
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FLETCHER_CYCLE
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} fletcher_4_impl_chosen = FLETCHER_SCALAR;
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@ -190,6 +196,9 @@ static struct fletcher_4_impl_selector {
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#if defined(HAVE_AVX) && defined(HAVE_AVX2)
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[ FLETCHER_AVX2 ] = { "avx2", &fletcher_4_avx2_ops },
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#endif
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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[ FLETCHER_AVX512F ] = { "avx512f", &fletcher_4_avx512f_ops },
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#endif
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#if !defined(_KERNEL)
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[ FLETCHER_CYCLE ] = { "cycle", &fletcher_4_scalar_ops }
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#endif
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@ -354,7 +363,7 @@ fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
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{
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const fletcher_4_ops_t *ops;
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if (IS_P2ALIGNED(size, 4 * sizeof (uint32_t)))
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if (IS_P2ALIGNED(size, 8 * sizeof (uint32_t)))
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ops = fletcher_4_impl_get();
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else
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ops = &fletcher_4_scalar_ops;
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@ -370,7 +379,7 @@ fletcher_4_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
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{
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const fletcher_4_ops_t *ops;
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if (IS_P2ALIGNED(size, 4 * sizeof (uint32_t)))
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if (IS_P2ALIGNED(size, 8 * sizeof (uint32_t)))
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ops = fletcher_4_impl_get();
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else
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ops = &fletcher_4_scalar_ops;
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157
module/zcommon/zfs_fletcher_avx512.c
Normal file
157
module/zcommon/zfs_fletcher_avx512.c
Normal file
@ -0,0 +1,157 @@
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/*
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* CDDL HEADER START
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*
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* The contents of this file are subject to the terms of the
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* Common Development and Distribution License (the "License").
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* You may not use this file except in compliance with the License.
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*
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* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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* or http://www.opensolaris.org/os/licensing.
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* See the License for the specific language governing permissions
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* and limitations under the License.
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*
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* When distributing Covered Code, include this CDDL HEADER in each
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* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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* If applicable, add the following below this CDDL HEADER, with the
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* fields enclosed by brackets "[]" replaced with your own identifying
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* information: Portions Copyright [yyyy] [name of copyright owner]
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*
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* CDDL HEADER END
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*/
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/*
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* Copyright (C) 2016 Gvozden Nešković. All rights reserved.
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*/
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#if defined(__x86_64) && defined(HAVE_AVX512F)
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#include <linux/simd_x86.h>
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#include <sys/byteorder.h>
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#include <sys/spa_checksum.h>
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#include <zfs_fletcher.h>
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#define __asm __asm__ __volatile__
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typedef struct {
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uint64_t v[8] __attribute__((aligned(64)));
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} zfs_avx512_t;
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static void
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fletcher_4_avx512f_init(zio_cksum_t *zcp)
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{
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kfpu_begin();
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/* clear registers */
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__asm("vpxorq %zmm0, %zmm0, %zmm0");
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__asm("vpxorq %zmm1, %zmm1, %zmm1");
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__asm("vpxorq %zmm2, %zmm2, %zmm2");
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__asm("vpxorq %zmm3, %zmm3, %zmm3");
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}
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static void
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fletcher_4_avx512f(const void *buf, uint64_t size, zio_cksum_t *unused)
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{
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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for (; ip < ipend; ip += 8) {
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__asm("vpmovzxdq %0, %%zmm4"::"m" (*ip));
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__asm("vpaddq %zmm4, %zmm0, %zmm0");
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__asm("vpaddq %zmm0, %zmm1, %zmm1");
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__asm("vpaddq %zmm1, %zmm2, %zmm2");
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__asm("vpaddq %zmm2, %zmm3, %zmm3");
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}
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}
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static void
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fletcher_4_avx512f_byteswap(const void *buf, uint64_t size, zio_cksum_t *unused)
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{
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static const uint64_t byteswap_mask = 0xFFULL;
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const uint32_t *ip = buf;
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const uint32_t *ipend = (uint32_t *)((uint8_t *)ip + size);
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__asm("vpbroadcastq %0, %%zmm8" :: "r" (byteswap_mask));
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__asm("vpsllq $8, %zmm8, %zmm9");
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__asm("vpsllq $16, %zmm8, %zmm10");
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__asm("vpsllq $24, %zmm8, %zmm11");
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for (; ip < ipend; ip += 8) {
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__asm("vpmovzxdq %0, %%zmm5"::"m" (*ip));
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__asm("vpsrlq $24, %zmm5, %zmm6");
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__asm("vpandd %zmm8, %zmm6, %zmm6");
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__asm("vpsrlq $8, %zmm5, %zmm7");
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__asm("vpandd %zmm9, %zmm7, %zmm7");
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__asm("vpord %zmm6, %zmm7, %zmm4");
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__asm("vpsllq $8, %zmm5, %zmm6");
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__asm("vpandd %zmm10, %zmm6, %zmm6");
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__asm("vpord %zmm6, %zmm4, %zmm4");
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__asm("vpsllq $24, %zmm5, %zmm5");
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__asm("vpandd %zmm11, %zmm5, %zmm5");
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__asm("vpord %zmm5, %zmm4, %zmm4");
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__asm("vpaddq %zmm4, %zmm0, %zmm0");
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__asm("vpaddq %zmm0, %zmm1, %zmm1");
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__asm("vpaddq %zmm1, %zmm2, %zmm2");
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__asm("vpaddq %zmm2, %zmm3, %zmm3");
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}
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}
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static void
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fletcher_4_avx512f_fini(zio_cksum_t *zcp)
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{
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static const uint64_t
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CcA[] = { 0, 0, 1, 3, 6, 10, 15, 21 },
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CcB[] = { 28, 36, 44, 52, 60, 68, 76, 84 },
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DcA[] = { 0, 0, 0, 1, 4, 10, 20, 35 },
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DcB[] = { 56, 84, 120, 164, 216, 276, 344, 420 },
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DcC[] = { 448, 512, 576, 640, 704, 768, 832, 896 };
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zfs_avx512_t a, b, c, b8, c64, d512;
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uint64_t A, B, C, D;
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uint64_t i;
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__asm("vmovdqu64 %%zmm0, %0":"=m" (a));
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__asm("vmovdqu64 %%zmm1, %0":"=m" (b));
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__asm("vmovdqu64 %%zmm2, %0":"=m" (c));
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__asm("vpsllq $3, %zmm1, %zmm1");
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__asm("vpsllq $6, %zmm2, %zmm2");
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__asm("vpsllq $9, %zmm3, %zmm3");
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__asm("vmovdqu64 %%zmm1, %0":"=m" (b8));
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__asm("vmovdqu64 %%zmm2, %0":"=m" (c64));
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__asm("vmovdqu64 %%zmm3, %0":"=m" (d512));
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kfpu_end();
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A = a.v[0];
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B = b8.v[0];
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C = c64.v[0] - CcB[0] * b.v[0];
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D = d512.v[0] - DcC[0] * c.v[0] + DcB[0] * b.v[0];
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for (i = 1; i < 8; i++) {
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A += a.v[i];
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B += b8.v[i] - i * a.v[i];
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C += c64.v[i] - CcB[i] * b.v[i] + CcA[i] * a.v[i];
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D += d512.v[i] - DcC[i] * c.v[i] + DcB[i] * b.v[i] -
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DcA[i] * a.v[i];
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}
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ZIO_SET_CHECKSUM(zcp, A, B, C, D);
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}
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static boolean_t
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fletcher_4_avx512f_valid(void)
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{
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return (zfs_avx512f_available());
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}
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const fletcher_4_ops_t fletcher_4_avx512f_ops = {
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.init = fletcher_4_avx512f_init,
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.fini = fletcher_4_avx512f_fini,
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.compute = fletcher_4_avx512f,
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.compute_byteswap = fletcher_4_avx512f_byteswap,
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.valid = fletcher_4_avx512f_valid,
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.name = "avx512f"
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};
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#endif /* defined(__x86_64) && defined(HAVE_AVX512F) */
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