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ABD raidz avx512f support

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Implement shift based multiplication for 512f. Higher IPC over lookup based
methods yields up to 40% better performance on the current hardware.

Results on Xeon Phi(TM) CPU 7210:
implementation   gen_p           gen_pq          gen_pqr         rec_p           rec_q           rec_r           rec_pq          rec_pr          rec_qr          rec_pqr
original         142232671       24411492        12948205        283053705       22348167        4215911         9171609         2265548         2378370         1648495
scalar           295711162       49851491        33253815        293198109       88179448        61866752        27941684        25764416        17384442        12138153
sse2             410055998       199642658       117973654       406240463       152688682       121092250       84968180        79291076        47473657        20779719
ssse3            411641595       199669571       117937647       406211024       137638508       117050346       81263322        76120405        46281559        32696722
avx2             616485806       311515332       188595628       605455115       260602390       230554476       148198817       138800254       92273356        62937819
avx512f          832191523       408509425       253599522       810094481       404325734       317590971       218235687       197204920       133101937       94001219
fastest          avx512f         avx512f         avx512f         avx512f         avx512f         avx512f         avx512f         avx512f         avx512f         avx512f

Signed-off-by: Gvozden Neskovic <neskovic@gmail.com>
This commit is contained in:
Gvozden Neskovic
2016-11-20 06:01:31 +01:00
committed by Brian Behlendorf
parent cbf484f8ad
commit 65d71d4212
7 changed files with 252 additions and 399 deletions
Download Patch File Download Diff File Expand all files Collapse all files
module/zfs/vdev_raidz_math_sse2.c
+8 -30
View File
@@ -58,9 +58,6 @@ typedef struct v {
uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
} v_t;
#define PREFETCHNTA(ptr, offset) {}
#define PREFETCH(ptr, offset) {}
#define XOR_ACC(src, r...) \
{ \
switch (REG_CNT(r)) { \
@@ -106,27 +103,8 @@ typedef struct v {
break; \
} \
}
#define ZERO(r...) \
{ \
switch (REG_CNT(r)) { \
case 4: \
__asm( \
"pxor %" VR0(r) ", %" VR0(r) "\n" \
"pxor %" VR1(r) ", %" VR1(r) "\n" \
"pxor %" VR2(r) ", %" VR2(r) "\n" \
"pxor %" VR3(r) ", %" VR3(r)); \
break; \
case 2: \
__asm( \
"pxor %" VR0(r) ", %" VR0(r) "\n" \
"pxor %" VR1(r) ", %" VR1(r)); \
break; \
case 1: \
__asm( \
"pxor %" VR0(r) ", %" VR0(r)); \
break; \
} \
}
#define ZERO(r...) XOR(r, r)
#define COPY(r...) \
{ \
@@ -259,7 +237,7 @@ typedef struct v {
#define _MUL_PARAM(x, in, acc) \
{ \
if (x & 0x01) { COPY(in, acc); } else { XOR(acc, acc); } \
if (x & 0x01) { COPY(in, acc); } else { ZERO(acc); } \
if (x & 0xfe) { MUL2(in); } \
if (x & 0x02) { XOR(in, acc); } \
if (x & 0xfc) { MUL2(in); } \
@@ -552,7 +530,7 @@ gf_x2_mul_fns[256] = {
#define ADD_D 0, 1, 2, 3
#define MUL_STRIDE 2
#define MUL_DEFINE() {}
#define MUL_DEFINE() MUL2_SETUP()
#define MUL_D 0, 1
#define GEN_P_STRIDE 4
@@ -582,7 +560,7 @@ gf_x2_mul_fns[256] = {
#define SYN_PQ_X 4, 5, 6, 7
#define REC_PQ_STRIDE 2
#define REC_PQ_DEFINE() {}
#define REC_PQ_DEFINE() MUL2_SETUP()
#define REC_PQ_X 0, 1
#define REC_PQ_Y 2, 3
#define REC_PQ_T 4, 5
@@ -592,7 +570,7 @@ gf_x2_mul_fns[256] = {
#define SYN_PR_X 4, 5, 6, 7
#define REC_PR_STRIDE 2
#define REC_PR_DEFINE() {}
#define REC_PR_DEFINE() MUL2_SETUP()
#define REC_PR_X 0, 1
#define REC_PR_Y 2, 3
#define REC_PR_T 4, 5
@@ -602,7 +580,7 @@ gf_x2_mul_fns[256] = {
#define SYN_QR_X 4, 5, 6, 7
#define REC_QR_STRIDE 2
#define REC_QR_DEFINE() {}
#define REC_QR_DEFINE() MUL2_SETUP()
#define REC_QR_X 0, 1
#define REC_QR_Y 2, 3
#define REC_QR_T 4, 5
@@ -612,7 +590,7 @@ gf_x2_mul_fns[256] = {
#define SYN_PQR_X 4, 5, 6, 7
#define REC_PQR_STRIDE 1
#define REC_PQR_DEFINE() {}
#define REC_PQR_DEFINE() MUL2_SETUP()
#define REC_PQR_X 0
#define REC_PQR_Y 1
#define REC_PQR_Z 2