Preliminary support for RV64G

This adds basic support for RISC-V, specifically RV64G.

Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov>
Signed-off-by: Romain Dolbeau <romain.dolbeau@european-processor-initiative.eu>
Closes #9540
This commit is contained in:
Romain Dolbeau
2019-11-06 19:56:09 +01:00
committed by Brian Behlendorf
parent 27ece2ee4d
commit 4254e40729
6 changed files with 138 additions and 3 deletions
+20 -1
View File
@@ -192,10 +192,29 @@ extern "C" {
#define _SUNOS_VTOC_16
/*
* RISC-V arch specific defines
* only RV64G (including atomic) LP64 is supported yetxi
*/
#elif defined(__riscv) && defined(_LP64) && _LP64 && \
defined(__riscv_atomic) && __riscv_atomic
#ifndef __riscv__
#define __riscv__
#endif
#ifndef __rv64g__
#define __rv64g__
#endif
#define _LITTLE_ENDIAN
#define _SUNOS_VTOC_16
#else
/*
* Currently supported:
* x86_64, i386, arm, powerpc, s390, sparc, and mips
* x86_64, i386, arm, powerpc, s390, sparc, mips, and RV64G
*/
#error "Unsupported ISA type"
#endif