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ICP: gcm-avx: Support architectures lacking the MOVBE instruction
There are a couple of x86_64 architectures which support all needed features to make the accelerated GCM implementation work but the MOVBE instruction. Those are mainly Intel Sandy- and Ivy-Bridge and AMD Bulldozer, Piledriver, and Steamroller. By using MOVBE only if available and replacing it with a MOV followed by a BSWAP if not, those architectures now benefit from the new GCM routines and performance is considerably better compared to the original implementation. Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov> Reviewed-by: Adam D. Moss <c@yotes.com> Signed-off-by: Attila Fülöp <attila@fueloep.org> Followup #9749 Closes #10029
This commit is contained in:
Attila Fülöp
Tony Hutter
parent
76354f945e
commit
3d09d3809b
@ -50,6 +50,8 @@ static uint32_t icp_gcm_impl = IMPL_FASTEST;
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static uint32_t user_sel_impl = IMPL_FASTEST;
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#ifdef CAN_USE_GCM_ASM
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/* Does the architecture we run on support the MOVBE instruction? */
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boolean_t gcm_avx_can_use_movbe = B_FALSE;
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/*
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* Whether to use the optimized openssl gcm and ghash implementations.
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* Set to true if module parameter icp_gcm_impl == "avx".
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@ -60,6 +62,7 @@ static boolean_t gcm_use_avx = B_FALSE;
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static inline boolean_t gcm_avx_will_work(void);
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static inline void gcm_set_avx(boolean_t);
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static inline boolean_t gcm_toggle_avx(void);
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extern boolean_t atomic_toggle_boolean_nv(volatile boolean_t *);
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static int gcm_mode_encrypt_contiguous_blocks_avx(gcm_ctx_t *, char *, size_t,
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crypto_data_t *, size_t);
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@ -618,19 +621,28 @@ gcm_init_ctx(gcm_ctx_t *gcm_ctx, char *param, size_t block_size,
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}
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#ifdef CAN_USE_GCM_ASM
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/*
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* Handle the "cycle" implementation by creating avx and non avx
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* contexts alternately.
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*/
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if (GCM_IMPL_READ(icp_gcm_impl) != IMPL_CYCLE) {
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gcm_ctx->gcm_use_avx = GCM_IMPL_USE_AVX;
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} else {
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/*
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* Handle the "cycle" implementation by creating avx and
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* non-avx contexts alternately.
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*/
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gcm_ctx->gcm_use_avx = gcm_toggle_avx();
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}
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/* We don't handle byte swapped key schedules in the avx code path. */
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aes_key_t *ks = (aes_key_t *)gcm_ctx->gcm_keysched;
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if (ks->ops->needs_byteswap == B_TRUE) {
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gcm_ctx->gcm_use_avx = B_FALSE;
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/*
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* We don't handle byte swapped key schedules in the avx
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* code path.
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*/
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aes_key_t *ks = (aes_key_t *)gcm_ctx->gcm_keysched;
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if (ks->ops->needs_byteswap == B_TRUE) {
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gcm_ctx->gcm_use_avx = B_FALSE;
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}
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/* Use the MOVBE and the BSWAP variants alternately. */
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if (gcm_ctx->gcm_use_avx == B_TRUE &&
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zfs_movbe_available() == B_TRUE) {
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(void) atomic_toggle_boolean_nv(
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(volatile boolean_t *)&gcm_avx_can_use_movbe);
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}
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}
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/* Avx and non avx context initialization differs from here on. */
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if (gcm_ctx->gcm_use_avx == B_FALSE) {
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@ -852,9 +864,15 @@ gcm_impl_init(void)
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* Use the avx implementation if it's available and the implementation
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* hasn't changed from its default value of fastest on module load.
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*/
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if (gcm_avx_will_work() &&
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GCM_IMPL_READ(user_sel_impl) == IMPL_FASTEST) {
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gcm_set_avx(B_TRUE);
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if (gcm_avx_will_work()) {
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#ifdef HAVE_MOVBE
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if (zfs_movbe_available() == B_TRUE) {
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atomic_swap_32(&gcm_avx_can_use_movbe, B_TRUE);
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}
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#endif
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if (GCM_IMPL_READ(user_sel_impl) == IMPL_FASTEST) {
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gcm_set_avx(B_TRUE);
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}
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}
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#endif
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/* Finish initialization */
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@ -1029,7 +1047,6 @@ MODULE_PARM_DESC(icp_gcm_impl, "Select gcm implementation.");
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static uint32_t gcm_avx_chunk_size =
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((32 * 1024) / GCM_AVX_MIN_DECRYPT_BYTES) * GCM_AVX_MIN_DECRYPT_BYTES;
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extern boolean_t atomic_toggle_boolean_nv(volatile boolean_t *);
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extern void clear_fpu_regs_avx(void);
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extern void gcm_xor_avx(const uint8_t *src, uint8_t *dst);
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extern void aes_encrypt_intel(const uint32_t rk[], int nr,
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@ -1050,8 +1067,8 @@ gcm_avx_will_work(void)
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{
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/* Avx should imply aes-ni and pclmulqdq, but make sure anyhow. */
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return (kfpu_allowed() &&
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zfs_avx_available() && zfs_movbe_available() &&
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zfs_aes_available() && zfs_pclmulqdq_available());
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zfs_avx_available() && zfs_aes_available() &&
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zfs_pclmulqdq_available());
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}
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static inline void
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@ -45,10 +45,13 @@
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# upstream merges.
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#if defined(__x86_64__) && defined(HAVE_AVX) && \
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defined(HAVE_AES) && defined(HAVE_PCLMULQDQ) && defined(HAVE_MOVBE)
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defined(HAVE_AES) && defined(HAVE_PCLMULQDQ)
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.extern gcm_avx_can_use_movbe
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.text
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#ifdef HAVE_MOVBE
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.type _aesni_ctr32_ghash_6x,@function
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.align 32
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_aesni_ctr32_ghash_6x:
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@ -361,6 +364,333 @@ _aesni_ctr32_ghash_6x:
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.byte 0xf3,0xc3
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.size _aesni_ctr32_ghash_6x,.-_aesni_ctr32_ghash_6x
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#endif /* ifdef HAVE_MOVBE */
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.type _aesni_ctr32_ghash_no_movbe_6x,@function
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.align 32
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_aesni_ctr32_ghash_no_movbe_6x:
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vmovdqu 32(%r11),%xmm2
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subq $6,%rdx
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vpxor %xmm4,%xmm4,%xmm4
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vmovdqu 0-128(%rcx),%xmm15
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vpaddb %xmm2,%xmm1,%xmm10
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vpaddb %xmm2,%xmm10,%xmm11
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vpaddb %xmm2,%xmm11,%xmm12
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vpaddb %xmm2,%xmm12,%xmm13
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vpaddb %xmm2,%xmm13,%xmm14
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vpxor %xmm15,%xmm1,%xmm9
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vmovdqu %xmm4,16+8(%rsp)
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jmp .Loop6x_nmb
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.align 32
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.Loop6x_nmb:
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addl $100663296,%ebx
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jc .Lhandle_ctr32_nmb
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vmovdqu 0-32(%r9),%xmm3
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vpaddb %xmm2,%xmm14,%xmm1
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vpxor %xmm15,%xmm10,%xmm10
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vpxor %xmm15,%xmm11,%xmm11
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.Lresume_ctr32_nmb:
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vmovdqu %xmm1,(%r8)
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vpclmulqdq $0x10,%xmm3,%xmm7,%xmm5
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vpxor %xmm15,%xmm12,%xmm12
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vmovups 16-128(%rcx),%xmm2
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vpclmulqdq $0x01,%xmm3,%xmm7,%xmm6
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xorq %r12,%r12
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cmpq %r14,%r15
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vaesenc %xmm2,%xmm9,%xmm9
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vmovdqu 48+8(%rsp),%xmm0
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vpxor %xmm15,%xmm13,%xmm13
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vpclmulqdq $0x00,%xmm3,%xmm7,%xmm1
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vaesenc %xmm2,%xmm10,%xmm10
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vpxor %xmm15,%xmm14,%xmm14
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setnc %r12b
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vpclmulqdq $0x11,%xmm3,%xmm7,%xmm7
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vaesenc %xmm2,%xmm11,%xmm11
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vmovdqu 16-32(%r9),%xmm3
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negq %r12
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vaesenc %xmm2,%xmm12,%xmm12
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vpxor %xmm5,%xmm6,%xmm6
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vpclmulqdq $0x00,%xmm3,%xmm0,%xmm5
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vpxor %xmm4,%xmm8,%xmm8
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vaesenc %xmm2,%xmm13,%xmm13
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vpxor %xmm5,%xmm1,%xmm4
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andq $0x60,%r12
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vmovups 32-128(%rcx),%xmm15
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vpclmulqdq $0x10,%xmm3,%xmm0,%xmm1
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vaesenc %xmm2,%xmm14,%xmm14
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vpclmulqdq $0x01,%xmm3,%xmm0,%xmm2
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leaq (%r14,%r12,1),%r14
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor 16+8(%rsp),%xmm8,%xmm8
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vpclmulqdq $0x11,%xmm3,%xmm0,%xmm3
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vmovdqu 64+8(%rsp),%xmm0
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vaesenc %xmm15,%xmm10,%xmm10
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movq 88(%r14),%r13
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bswapq %r13
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vaesenc %xmm15,%xmm11,%xmm11
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movq 80(%r14),%r12
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bswapq %r12
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vaesenc %xmm15,%xmm12,%xmm12
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movq %r13,32+8(%rsp)
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vaesenc %xmm15,%xmm13,%xmm13
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movq %r12,40+8(%rsp)
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vmovdqu 48-32(%r9),%xmm5
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vaesenc %xmm15,%xmm14,%xmm14
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vmovups 48-128(%rcx),%xmm15
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vpxor %xmm1,%xmm6,%xmm6
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vpclmulqdq $0x00,%xmm5,%xmm0,%xmm1
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor %xmm2,%xmm6,%xmm6
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vpclmulqdq $0x10,%xmm5,%xmm0,%xmm2
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vaesenc %xmm15,%xmm10,%xmm10
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vpxor %xmm3,%xmm7,%xmm7
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vpclmulqdq $0x01,%xmm5,%xmm0,%xmm3
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vaesenc %xmm15,%xmm11,%xmm11
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vpclmulqdq $0x11,%xmm5,%xmm0,%xmm5
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vmovdqu 80+8(%rsp),%xmm0
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vaesenc %xmm15,%xmm12,%xmm12
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vaesenc %xmm15,%xmm13,%xmm13
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vpxor %xmm1,%xmm4,%xmm4
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vmovdqu 64-32(%r9),%xmm1
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vaesenc %xmm15,%xmm14,%xmm14
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vmovups 64-128(%rcx),%xmm15
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vpxor %xmm2,%xmm6,%xmm6
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vpclmulqdq $0x00,%xmm1,%xmm0,%xmm2
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor %xmm3,%xmm6,%xmm6
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vpclmulqdq $0x10,%xmm1,%xmm0,%xmm3
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vaesenc %xmm15,%xmm10,%xmm10
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movq 72(%r14),%r13
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bswapq %r13
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vpxor %xmm5,%xmm7,%xmm7
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vpclmulqdq $0x01,%xmm1,%xmm0,%xmm5
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vaesenc %xmm15,%xmm11,%xmm11
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movq 64(%r14),%r12
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bswapq %r12
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vpclmulqdq $0x11,%xmm1,%xmm0,%xmm1
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vmovdqu 96+8(%rsp),%xmm0
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vaesenc %xmm15,%xmm12,%xmm12
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movq %r13,48+8(%rsp)
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vaesenc %xmm15,%xmm13,%xmm13
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movq %r12,56+8(%rsp)
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vpxor %xmm2,%xmm4,%xmm4
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vmovdqu 96-32(%r9),%xmm2
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vaesenc %xmm15,%xmm14,%xmm14
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vmovups 80-128(%rcx),%xmm15
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vpxor %xmm3,%xmm6,%xmm6
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vpclmulqdq $0x00,%xmm2,%xmm0,%xmm3
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor %xmm5,%xmm6,%xmm6
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vpclmulqdq $0x10,%xmm2,%xmm0,%xmm5
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vaesenc %xmm15,%xmm10,%xmm10
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movq 56(%r14),%r13
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bswapq %r13
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vpxor %xmm1,%xmm7,%xmm7
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vpclmulqdq $0x01,%xmm2,%xmm0,%xmm1
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vpxor 112+8(%rsp),%xmm8,%xmm8
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vaesenc %xmm15,%xmm11,%xmm11
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movq 48(%r14),%r12
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bswapq %r12
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vpclmulqdq $0x11,%xmm2,%xmm0,%xmm2
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vaesenc %xmm15,%xmm12,%xmm12
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movq %r13,64+8(%rsp)
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vaesenc %xmm15,%xmm13,%xmm13
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movq %r12,72+8(%rsp)
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vpxor %xmm3,%xmm4,%xmm4
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vmovdqu 112-32(%r9),%xmm3
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vaesenc %xmm15,%xmm14,%xmm14
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vmovups 96-128(%rcx),%xmm15
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vpxor %xmm5,%xmm6,%xmm6
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vpclmulqdq $0x10,%xmm3,%xmm8,%xmm5
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor %xmm1,%xmm6,%xmm6
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vpclmulqdq $0x01,%xmm3,%xmm8,%xmm1
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vaesenc %xmm15,%xmm10,%xmm10
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movq 40(%r14),%r13
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bswapq %r13
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vpxor %xmm2,%xmm7,%xmm7
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vpclmulqdq $0x00,%xmm3,%xmm8,%xmm2
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vaesenc %xmm15,%xmm11,%xmm11
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movq 32(%r14),%r12
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bswapq %r12
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vpclmulqdq $0x11,%xmm3,%xmm8,%xmm8
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vaesenc %xmm15,%xmm12,%xmm12
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movq %r13,80+8(%rsp)
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vaesenc %xmm15,%xmm13,%xmm13
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movq %r12,88+8(%rsp)
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vpxor %xmm5,%xmm6,%xmm6
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vaesenc %xmm15,%xmm14,%xmm14
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vpxor %xmm1,%xmm6,%xmm6
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vmovups 112-128(%rcx),%xmm15
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vpslldq $8,%xmm6,%xmm5
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vpxor %xmm2,%xmm4,%xmm4
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vmovdqu 16(%r11),%xmm3
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vaesenc %xmm15,%xmm9,%xmm9
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vpxor %xmm8,%xmm7,%xmm7
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vaesenc %xmm15,%xmm10,%xmm10
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vpxor %xmm5,%xmm4,%xmm4
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movq 24(%r14),%r13
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bswapq %r13
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vaesenc %xmm15,%xmm11,%xmm11
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movq 16(%r14),%r12
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bswapq %r12
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vpalignr $8,%xmm4,%xmm4,%xmm0
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vpclmulqdq $0x10,%xmm3,%xmm4,%xmm4
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movq %r13,96+8(%rsp)
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vaesenc %xmm15,%xmm12,%xmm12
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movq %r12,104+8(%rsp)
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vaesenc %xmm15,%xmm13,%xmm13
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vmovups 128-128(%rcx),%xmm1
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vaesenc %xmm15,%xmm14,%xmm14
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vaesenc %xmm1,%xmm9,%xmm9
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vmovups 144-128(%rcx),%xmm15
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vaesenc %xmm1,%xmm10,%xmm10
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vpsrldq $8,%xmm6,%xmm6
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vaesenc %xmm1,%xmm11,%xmm11
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vpxor %xmm6,%xmm7,%xmm7
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vaesenc %xmm1,%xmm12,%xmm12
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vpxor %xmm0,%xmm4,%xmm4
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movq 8(%r14),%r13
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bswapq %r13
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vaesenc %xmm1,%xmm13,%xmm13
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movq 0(%r14),%r12
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bswapq %r12
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vaesenc %xmm1,%xmm14,%xmm14
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vmovups 160-128(%rcx),%xmm1
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cmpl $12,%ebp // ICP uses 10,12,14 not 9,11,13 for rounds.
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jb .Lenc_tail_nmb
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vaesenc %xmm15,%xmm9,%xmm9
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vaesenc %xmm15,%xmm10,%xmm10
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vaesenc %xmm15,%xmm11,%xmm11
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vaesenc %xmm15,%xmm12,%xmm12
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vaesenc %xmm15,%xmm13,%xmm13
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vaesenc %xmm15,%xmm14,%xmm14
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vaesenc %xmm1,%xmm9,%xmm9
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vaesenc %xmm1,%xmm10,%xmm10
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vaesenc %xmm1,%xmm11,%xmm11
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vaesenc %xmm1,%xmm12,%xmm12
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vaesenc %xmm1,%xmm13,%xmm13
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vmovups 176-128(%rcx),%xmm15
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vaesenc %xmm1,%xmm14,%xmm14
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vmovups 192-128(%rcx),%xmm1
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cmpl $14,%ebp // ICP does not zero key schedule.
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jb .Lenc_tail_nmb
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vaesenc %xmm15,%xmm9,%xmm9
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vaesenc %xmm15,%xmm10,%xmm10
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vaesenc %xmm15,%xmm11,%xmm11
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vaesenc %xmm15,%xmm12,%xmm12
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vaesenc %xmm15,%xmm13,%xmm13
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vaesenc %xmm15,%xmm14,%xmm14
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vaesenc %xmm1,%xmm9,%xmm9
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vaesenc %xmm1,%xmm10,%xmm10
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vaesenc %xmm1,%xmm11,%xmm11
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vaesenc %xmm1,%xmm12,%xmm12
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vaesenc %xmm1,%xmm13,%xmm13
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vmovups 208-128(%rcx),%xmm15
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vaesenc %xmm1,%xmm14,%xmm14
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vmovups 224-128(%rcx),%xmm1
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jmp .Lenc_tail_nmb
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.align 32
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.Lhandle_ctr32_nmb:
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vmovdqu (%r11),%xmm0
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vpshufb %xmm0,%xmm1,%xmm6
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vmovdqu 48(%r11),%xmm5
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vpaddd 64(%r11),%xmm6,%xmm10
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vpaddd %xmm5,%xmm6,%xmm11
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vmovdqu 0-32(%r9),%xmm3
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vpaddd %xmm5,%xmm10,%xmm12
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vpshufb %xmm0,%xmm10,%xmm10
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vpaddd %xmm5,%xmm11,%xmm13
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vpshufb %xmm0,%xmm11,%xmm11
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vpxor %xmm15,%xmm10,%xmm10
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vpaddd %xmm5,%xmm12,%xmm14
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vpshufb %xmm0,%xmm12,%xmm12
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vpxor %xmm15,%xmm11,%xmm11
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vpaddd %xmm5,%xmm13,%xmm1
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vpshufb %xmm0,%xmm13,%xmm13
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vpshufb %xmm0,%xmm14,%xmm14
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vpshufb %xmm0,%xmm1,%xmm1
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jmp .Lresume_ctr32_nmb
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.align 32
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.Lenc_tail_nmb:
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vaesenc %xmm15,%xmm9,%xmm9
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vmovdqu %xmm7,16+8(%rsp)
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vpalignr $8,%xmm4,%xmm4,%xmm8
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vaesenc %xmm15,%xmm10,%xmm10
|
||||
vpclmulqdq $0x10,%xmm3,%xmm4,%xmm4
|
||||
vpxor 0(%rdi),%xmm1,%xmm2
|
||||
vaesenc %xmm15,%xmm11,%xmm11
|
||||
vpxor 16(%rdi),%xmm1,%xmm0
|
||||
vaesenc %xmm15,%xmm12,%xmm12
|
||||
vpxor 32(%rdi),%xmm1,%xmm5
|
||||
vaesenc %xmm15,%xmm13,%xmm13
|
||||
vpxor 48(%rdi),%xmm1,%xmm6
|
||||
vaesenc %xmm15,%xmm14,%xmm14
|
||||
vpxor 64(%rdi),%xmm1,%xmm7
|
||||
vpxor 80(%rdi),%xmm1,%xmm3
|
||||
vmovdqu (%r8),%xmm1
|
||||
|
||||
vaesenclast %xmm2,%xmm9,%xmm9
|
||||
vmovdqu 32(%r11),%xmm2
|
||||
vaesenclast %xmm0,%xmm10,%xmm10
|
||||
vpaddb %xmm2,%xmm1,%xmm0
|
||||
movq %r13,112+8(%rsp)
|
||||
leaq 96(%rdi),%rdi
|
||||
vaesenclast %xmm5,%xmm11,%xmm11
|
||||
vpaddb %xmm2,%xmm0,%xmm5
|
||||
movq %r12,120+8(%rsp)
|
||||
leaq 96(%rsi),%rsi
|
||||
vmovdqu 0-128(%rcx),%xmm15
|
||||
vaesenclast %xmm6,%xmm12,%xmm12
|
||||
vpaddb %xmm2,%xmm5,%xmm6
|
||||
vaesenclast %xmm7,%xmm13,%xmm13
|
||||
vpaddb %xmm2,%xmm6,%xmm7
|
||||
vaesenclast %xmm3,%xmm14,%xmm14
|
||||
vpaddb %xmm2,%xmm7,%xmm3
|
||||
|
||||
addq $0x60,%r10
|
||||
subq $0x6,%rdx
|
||||
jc .L6x_done_nmb
|
||||
|
||||
vmovups %xmm9,-96(%rsi)
|
||||
vpxor %xmm15,%xmm1,%xmm9
|
||||
vmovups %xmm10,-80(%rsi)
|
||||
vmovdqa %xmm0,%xmm10
|
||||
vmovups %xmm11,-64(%rsi)
|
||||
vmovdqa %xmm5,%xmm11
|
||||
vmovups %xmm12,-48(%rsi)
|
||||
vmovdqa %xmm6,%xmm12
|
||||
vmovups %xmm13,-32(%rsi)
|
||||
vmovdqa %xmm7,%xmm13
|
||||
vmovups %xmm14,-16(%rsi)
|
||||
vmovdqa %xmm3,%xmm14
|
||||
vmovdqu 32+8(%rsp),%xmm7
|
||||
jmp .Loop6x_nmb
|
||||
|
||||
.L6x_done_nmb:
|
||||
vpxor 16+8(%rsp),%xmm8,%xmm8
|
||||
vpxor %xmm4,%xmm8,%xmm8
|
||||
|
||||
.byte 0xf3,0xc3
|
||||
.size _aesni_ctr32_ghash_no_movbe_6x,.-_aesni_ctr32_ghash_no_movbe_6x
|
||||
|
||||
.globl aesni_gcm_decrypt
|
||||
.type aesni_gcm_decrypt,@function
|
||||
.align 32
|
||||
@ -431,8 +761,19 @@ aesni_gcm_decrypt:
|
||||
vmovdqu %xmm2,96(%rsp)
|
||||
vmovdqu %xmm3,112(%rsp)
|
||||
|
||||
#ifdef HAVE_MOVBE
|
||||
#ifdef _KERNEL
|
||||
testl $1,gcm_avx_can_use_movbe(%rip)
|
||||
#else
|
||||
testl $1,gcm_avx_can_use_movbe@GOTPCREL(%rip)
|
||||
#endif
|
||||
jz 1f
|
||||
call _aesni_ctr32_ghash_6x
|
||||
|
||||
jmp 2f
|
||||
1:
|
||||
#endif
|
||||
call _aesni_ctr32_ghash_no_movbe_6x
|
||||
2:
|
||||
vmovups %xmm9,-96(%rsi)
|
||||
vmovups %xmm10,-80(%rsi)
|
||||
vmovups %xmm11,-64(%rsi)
|
||||
@ -624,7 +965,19 @@ aesni_gcm_encrypt:
|
||||
movq $192,%r10
|
||||
vpshufb %xmm0,%xmm8,%xmm8
|
||||
|
||||
#ifdef HAVE_MOVBE
|
||||
#ifdef _KERNEL
|
||||
testl $1,gcm_avx_can_use_movbe(%rip)
|
||||
#else
|
||||
testl $1,gcm_avx_can_use_movbe@GOTPCREL(%rip)
|
||||
#endif
|
||||
jz 1f
|
||||
call _aesni_ctr32_ghash_6x
|
||||
jmp 2f
|
||||
1:
|
||||
#endif
|
||||
call _aesni_ctr32_ghash_no_movbe_6x
|
||||
2:
|
||||
vmovdqu 32(%rsp),%xmm7
|
||||
vmovdqu (%r11),%xmm0
|
||||
vmovdqu 0-32(%r9),%xmm3
|
||||
|
||||
@ -40,8 +40,9 @@ extern "C" {
|
||||
* anyhow.
|
||||
*/
|
||||
#if defined(__x86_64__) && defined(HAVE_AVX) && \
|
||||
defined(HAVE_AES) && defined(HAVE_PCLMULQDQ) && defined(HAVE_MOVBE)
|
||||
defined(HAVE_AES) && defined(HAVE_PCLMULQDQ)
|
||||
#define CAN_USE_GCM_ASM
|
||||
extern boolean_t gcm_avx_can_use_movbe;
|
||||
#endif
|
||||
|
||||
#define ECB_MODE 0x00000002
|
||||
|
||||
Loading…
Reference in New Issue
Block a user