Add AltiVec RAID-Z

Implements the RAID-Z function using AltiVec SIMD.
This is basically the NEON code translated to AltiVec.

Note that the 'fletcher' algorithm requires 64-bits
operations, and the initial implementations of AltiVec
(PPC74xx a.k.a. G4, PPC970 a.k.a. G5) only has up to
32-bits operations, so no 'fletcher'.

Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov>
Signed-off-by: Romain Dolbeau <romain.dolbeau@european-processor-initiative.eu>
Closes #9539
This commit is contained in:
Romain Dolbeau
2020-01-23 20:01:24 +01:00
committed by Brian Behlendorf
parent 1a69856034
commit 35b07497c6
12 changed files with 5200 additions and 1 deletions
+1
View File
@@ -3374,6 +3374,7 @@ Possible options are:
avx512bw - implementation using AVX512F & AVX512BW instruction sets (64bit x86 only)
aarch64_neon - implementation using NEON (Aarch64/64 bit ARMv8 only)
aarch64_neonx2 - implementation using NEON with more unrolling (Aarch64/64 bit ARMv8 only)
powerpc_altivec - implementation using Altivec (PowerPC only)
.sp
Default value: \fBfastest\fR.
.RE