Implementation of AVX2 optimized Fletcher-4

New functionality:
- Preserves existing scalar implementation.
- Adds AVX2 optimized Fletcher-4 computation.
- Fastest routines selected on module load (benchmark).
- Test case for Fletcher-4 added to ztest.

New zcommon module parameters:
-  zfs_fletcher_4_impl (str): selects the implementation to use.
    "fastest" - use the fastest version available
    "cycle"   - cycle trough all available impl for ztest
    "scalar"  - use the original version
    "avx2"    - new AVX2 implementation if available

Performance comparison (Intel i7 CPU, 1MB data buffers):
- Scalar:  4216 MB/s
- AVX2:   14499 MB/s

See contents of `/sys/module/zcommon/parameters/zfs_fletcher_4_impl`
to get list of supported values. If an implementation is not supported
on the system, it will not be shown. Currently selected option is
enclosed in `[]`.

Signed-off-by: Jinshan Xiong <jinshan.xiong@intel.com>
Signed-off-by: Andreas Dilger <andreas.dilger@intel.com>
Signed-off-by: Brian Behlendorf <behlendorf1@llnl.gov>
Closes #4330

module/zcommon/Makefile.in

@@ -15,3 +15,5 @@ $(MODULE)-objs += zfs_comutil.o
 $(MODULE)-objs += zfs_fletcher.o
 $(MODULE)-objs += zfs_uio.o
 $(MODULE)-objs += zpool_prop.o
+
+$(MODULE)-$(CONFIG_X86) += zfs_fletcher_intel.o

module/zcommon/zfs_fletcher.c

@@ -128,8 +128,60 @@
 #include <sys/types.h>
 #include <sys/sysmacros.h>
 #include <sys/byteorder.h>
-#include <sys/zio.h>
 #include <sys/spa.h>
+#include <sys/zfs_context.h>
+#include <zfs_fletcher.h>
+
+static void fletcher_4_scalar_init(zio_cksum_t *zcp);
+static void fletcher_4_scalar(const void *buf, uint64_t size,
+    zio_cksum_t *zcp);
+static void fletcher_4_scalar_byteswap(const void *buf, uint64_t size,
+    zio_cksum_t *zcp);
+static boolean_t fletcher_4_scalar_valid(void);
+
+static const fletcher_4_ops_t fletcher_4_scalar_ops = {
+	.init = fletcher_4_scalar_init,
+	.compute = fletcher_4_scalar,
+	.compute_byteswap = fletcher_4_scalar_byteswap,
+	.valid = fletcher_4_scalar_valid,
+	.name = "scalar"
+};
+
+static const fletcher_4_ops_t *fletcher_4_algos[] = {
+	&fletcher_4_scalar_ops,
+#if defined(HAVE_AVX) && defined(HAVE_AVX2)
+	&fletcher_4_avx2_ops,
+#endif
+};
+
+static enum fletcher_selector {
+	FLETCHER_FASTEST = 0,
+	FLETCHER_SCALAR,
+#if defined(HAVE_AVX) && defined(HAVE_AVX2)
+	FLETCHER_AVX2,
+#endif
+	FLETCHER_CYCLE
+} fletcher_4_impl_chosen = FLETCHER_SCALAR;
+
+static struct fletcher_4_impl_selector {
+	const char		*fis_name;
+	const fletcher_4_ops_t	*fis_ops;
+} fletcher_4_impl_selectors[] = {
+	[ FLETCHER_FASTEST ]	= { "fastest", NULL },
+	[ FLETCHER_SCALAR ]	= { "scalar", &fletcher_4_scalar_ops },
+#if defined(HAVE_AVX) && defined(HAVE_AVX2)
+	[ FLETCHER_AVX2 ]	= { "avx2", &fletcher_4_avx2_ops },
+#endif
+#if !defined(_KERNEL)
+	[ FLETCHER_CYCLE ]	= { "cycle", &fletcher_4_scalar_ops }
+#endif
+};
+
+static kmutex_t fletcher_4_impl_lock;
+
+static kstat_t *fletcher_4_kstat;
+
+static kstat_named_t fletcher_4_kstat_data[ARRAY_SIZE(fletcher_4_algos)];
 
 void
 fletcher_2_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
@@ -165,14 +217,24 @@ fletcher_2_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
 	ZIO_SET_CHECKSUM(zcp, a0, a1, b0, b1);
 }
 
-void
-fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
+static void fletcher_4_scalar_init(zio_cksum_t *zcp)
+{
+	ZIO_SET_CHECKSUM(zcp, 0, 0, 0, 0);
+}
+
+static void
+fletcher_4_scalar(const void *buf, uint64_t size, zio_cksum_t *zcp)
 {
 	const uint32_t *ip = buf;
 	const uint32_t *ipend = ip + (size / sizeof (uint32_t));
 	uint64_t a, b, c, d;
 
-	for (a = b = c = d = 0; ip < ipend; ip++) {
+	a = zcp->zc_word[0];
+	b = zcp->zc_word[1];
+	c = zcp->zc_word[2];
+	d = zcp->zc_word[3];
+
+	for (; ip < ipend; ip++) {
 		a += ip[0];
 		b += a;
 		c += b;
@@ -182,14 +244,19 @@ fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
 	ZIO_SET_CHECKSUM(zcp, a, b, c, d);
 }
 
-void
-fletcher_4_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
+static void
+fletcher_4_scalar_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
 {
 	const uint32_t *ip = buf;
 	const uint32_t *ipend = ip + (size / sizeof (uint32_t));
 	uint64_t a, b, c, d;
 
-	for (a = b = c = d = 0; ip < ipend; ip++) {
+	a = zcp->zc_word[0];
+	b = zcp->zc_word[1];
+	c = zcp->zc_word[2];
+	d = zcp->zc_word[3];
+
+	for (; ip < ipend; ip++) {
 		a += BSWAP_32(ip[0]);
 		b += a;
 		c += b;
@@ -199,53 +266,225 @@ fletcher_4_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
 	ZIO_SET_CHECKSUM(zcp, a, b, c, d);
 }
 
+static boolean_t
+fletcher_4_scalar_valid(void)
+{
+	return (B_TRUE);
+}
+
+int
+fletcher_4_impl_set(const char *val)
+{
+	const fletcher_4_ops_t *ops;
+	enum fletcher_selector idx;
+	size_t val_len;
+	unsigned i;
+
+	val_len = strlen(val);
+	while ((val_len > 0) && !!isspace(val[val_len-1])) /* trim '\n' */
+		val_len--;
+
+	for (i = 0; i < ARRAY_SIZE(fletcher_4_impl_selectors); i++) {
+		const char *name = fletcher_4_impl_selectors[i].fis_name;
+
+		if (val_len == strlen(name) &&
+		    strncmp(val, name, val_len) == 0) {
+			idx = i;
+			break;
+		}
+	}
+	if (i >= ARRAY_SIZE(fletcher_4_impl_selectors))
+		return (-EINVAL);
+
+	ops = fletcher_4_impl_selectors[idx].fis_ops;
+	if (ops == NULL || !ops->valid())
+		return (-ENOTSUP);
+
+	mutex_enter(&fletcher_4_impl_lock);
+	if (fletcher_4_impl_chosen != idx)
+		fletcher_4_impl_chosen = idx;
+	mutex_exit(&fletcher_4_impl_lock);
+
+	return (0);
+}
+
+static inline const fletcher_4_ops_t *
+fletcher_4_impl_get(void)
+{
+#if !defined(_KERNEL)
+	if (fletcher_4_impl_chosen == FLETCHER_CYCLE) {
+		static volatile unsigned int cycle_count = 0;
+		const fletcher_4_ops_t *ops = NULL;
+		unsigned int index;
+
+		while (1) {
+			index = atomic_inc_uint_nv(&cycle_count);
+			ops = fletcher_4_algos[
+			    index % ARRAY_SIZE(fletcher_4_algos)];
+			if (ops->valid())
+				break;
+		}
+		return (ops);
+	}
+#endif
+	membar_producer();
+	return (fletcher_4_impl_selectors[fletcher_4_impl_chosen].fis_ops);
+}
+
+void
+fletcher_4_native(const void *buf, uint64_t size, zio_cksum_t *zcp)
+{
+	const fletcher_4_ops_t *ops = fletcher_4_impl_get();
+
+	ops->init(zcp);
+	ops->compute(buf, size, zcp);
+	if (ops->fini != NULL)
+		ops->fini(zcp);
+}
+
+void
+fletcher_4_byteswap(const void *buf, uint64_t size, zio_cksum_t *zcp)
+{
+	const fletcher_4_ops_t *ops = fletcher_4_impl_get();
+
+	ops->init(zcp);
+	ops->compute_byteswap(buf, size, zcp);
+	if (ops->fini != NULL)
+		ops->fini(zcp);
+}
+
 void
 fletcher_4_incremental_native(const void *buf, uint64_t size,
     zio_cksum_t *zcp)
 {
-	const uint32_t *ip = buf;
-	const uint32_t *ipend = ip + (size / sizeof (uint32_t));
-	uint64_t a, b, c, d;
-
-	a = zcp->zc_word[0];
-	b = zcp->zc_word[1];
-	c = zcp->zc_word[2];
-	d = zcp->zc_word[3];
-
-	for (; ip < ipend; ip++) {
-		a += ip[0];
-		b += a;
-		c += b;
-		d += c;
-	}
-
-	ZIO_SET_CHECKSUM(zcp, a, b, c, d);
+	fletcher_4_scalar(buf, size, zcp);
 }
 
 void
 fletcher_4_incremental_byteswap(const void *buf, uint64_t size,
     zio_cksum_t *zcp)
 {
-	const uint32_t *ip = buf;
-	const uint32_t *ipend = ip + (size / sizeof (uint32_t));
-	uint64_t a, b, c, d;
+	fletcher_4_scalar_byteswap(buf, size, zcp);
+}
 
-	a = zcp->zc_word[0];
-	b = zcp->zc_word[1];
-	c = zcp->zc_word[2];
-	d = zcp->zc_word[3];
+void
+fletcher_4_init(void)
+{
+	const uint64_t const bench_ns = (50 * MICROSEC); /* 50ms */
+	unsigned long best_run_count = 0;
+	unsigned long best_run_index = 0;
+	const unsigned data_size = 4096;
+	char *databuf;
+	int i;
 
-	for (; ip < ipend; ip++) {
-		a += BSWAP_32(ip[0]);
-		b += a;
-		c += b;
-		d += c;
+	databuf = kmem_alloc(data_size, KM_SLEEP);
+	for (i = 0; i < ARRAY_SIZE(fletcher_4_algos); i++) {
+		const fletcher_4_ops_t *ops = fletcher_4_algos[i];
+		kstat_named_t *stat = &fletcher_4_kstat_data[i];
+		unsigned long run_count = 0;
+		hrtime_t start;
+		zio_cksum_t zc;
+
+		strncpy(stat->name, ops->name, sizeof (stat->name) - 1);
+		stat->data_type = KSTAT_DATA_UINT64;
+		stat->value.ui64 = 0;
+
+		if (!ops->valid())
+			continue;
+
+		kpreempt_disable();
+		start = gethrtime();
+		ops->init(&zc);
+		do {
+			ops->compute(databuf, data_size, &zc);
+			run_count++;
+		} while (gethrtime() < start + bench_ns);
+		if (ops->fini != NULL)
+			ops->fini(&zc);
+		kpreempt_enable();
+
+		if (run_count > best_run_count) {
+			best_run_count = run_count;
+			best_run_index = i;
+		}
+
+		/*
+		 * Due to high overhead of gethrtime(), the performance data
+		 * here is inaccurate and much slower than it could be.
+		 * It's fine for our use though because only relative speed
+		 * is important.
+		 */
+		stat->value.ui64 = data_size * run_count *
+		    (NANOSEC / bench_ns) >> 20; /* by MB/s */
 	}
+	kmem_free(databuf, data_size);
 
-	ZIO_SET_CHECKSUM(zcp, a, b, c, d);
+	fletcher_4_impl_selectors[FLETCHER_FASTEST].fis_ops =
+	    fletcher_4_algos[best_run_index];
+
+	mutex_init(&fletcher_4_impl_lock, NULL, MUTEX_DEFAULT, NULL);
+	fletcher_4_impl_set("fastest");
+
+	fletcher_4_kstat = kstat_create("zfs", 0, "fletcher_4_bench",
+	    "misc", KSTAT_TYPE_NAMED, ARRAY_SIZE(fletcher_4_algos),
+	    KSTAT_FLAG_VIRTUAL);
+	if (fletcher_4_kstat != NULL) {
+		fletcher_4_kstat->ks_data = fletcher_4_kstat_data;
+		kstat_install(fletcher_4_kstat);
+	}
+}
+
+void
+fletcher_4_fini(void)
+{
+	mutex_destroy(&fletcher_4_impl_lock);
+	if (fletcher_4_kstat != NULL) {
+		kstat_delete(fletcher_4_kstat);
+		fletcher_4_kstat = NULL;
+	}
 }
 
 #if defined(_KERNEL) && defined(HAVE_SPL)
+
+static int
+fletcher_4_param_get(char *buffer, struct kernel_param *unused)
+{
+	int i, cnt = 0;
+
+	for (i = 0; i < ARRAY_SIZE(fletcher_4_impl_selectors); i++) {
+		const fletcher_4_ops_t *ops;
+
+		ops = fletcher_4_impl_selectors[i].fis_ops;
+		if (!ops->valid())
+			continue;
+
+		cnt += sprintf(buffer + cnt,
+		    fletcher_4_impl_chosen == i ? "[%s] " : "%s ",
+		    fletcher_4_impl_selectors[i].fis_name);
+	}
+
+	return (cnt);
+}
+
+static int
+fletcher_4_param_set(const char *val, struct kernel_param *unused)
+{
+	return (fletcher_4_impl_set(val));
+}
+
+/*
+ * Choose a fletcher 4 implementation in ZFS.
+ * Users can choose the "fastest" algorithm, or "scalar" and "avx2" which means
+ * to compute fletcher 4 by CPU or vector instructions respectively.
+ * Users can also choose "cycle" to exercise all implementions, but this is
+ * for testing purpose therefore it can only be set in user space.
+ */
+module_param_call(zfs_fletcher_4_impl,
+    fletcher_4_param_set, fletcher_4_param_get, NULL, 0644);
+MODULE_PARM_DESC(zfs_fletcher_4_impl, "Select fletcher 4 algorithm");
+
+EXPORT_SYMBOL(fletcher_4_init);
+EXPORT_SYMBOL(fletcher_4_fini);
 EXPORT_SYMBOL(fletcher_2_native);
 EXPORT_SYMBOL(fletcher_2_byteswap);
 EXPORT_SYMBOL(fletcher_4_native);

module/zcommon/zfs_fletcher_intel.c

@@ -0,0 +1,148 @@
+/*
+ * Implement fast Fletcher4 with AVX2 instructions. (x86_64)
+ *
+ * Use the 256-bit AVX2 SIMD instructions and registers to compute
+ * Fletcher4 in four incremental 64-bit parallel accumulator streams,
+ * and then combine the streams to form the final four checksum words.
+ *
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * Authors:
+ *      James Guilford <james.guilford@intel.com>
+ *      Jinshan Xiong <jinshan.xiong@intel.com>
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#if defined(HAVE_AVX) && defined(HAVE_AVX2)
+
+#include <linux/simd_x86.h>
+#include <sys/spa_checksum.h>
+#include <zfs_fletcher.h>
+
+static void
+fletcher_4_avx2_init(zio_cksum_t *zcp)
+{
+	kfpu_begin();
+
+	/* clear avx2 registers */
+	asm volatile("vpxor %ymm0, %ymm0, %ymm0");
+	asm volatile("vpxor %ymm1, %ymm1, %ymm1");
+	asm volatile("vpxor %ymm2, %ymm2, %ymm2");
+	asm volatile("vpxor %ymm3, %ymm3, %ymm3");
+}
+
+static void
+fletcher_4_avx2_fini(zio_cksum_t *zcp)
+{
+	uint64_t __attribute__((aligned(32))) a[4];
+	uint64_t __attribute__((aligned(32))) b[4];
+	uint64_t __attribute__((aligned(32))) c[4];
+	uint64_t __attribute__((aligned(32))) d[4];
+	uint64_t A, B, C, D;
+
+	asm volatile("vmovdqu %%ymm0, %0":"=m" (a));
+	asm volatile("vmovdqu %%ymm1, %0":"=m" (b));
+	asm volatile("vmovdqu %%ymm2, %0":"=m" (c));
+	asm volatile("vmovdqu %%ymm3, %0":"=m" (d));
+	asm volatile("vzeroupper");
+
+	kfpu_end();
+
+	A = a[0] + a[1] + a[2] + a[3];
+	B = 0 - a[1] - 2*a[2] - 3*a[3]
+	    + 4*b[0] + 4*b[1] + 4*b[2] + 4*b[3];
+
+	C = a[2] + 3*a[3]
+	    -  6*b[0] - 10*b[1] - 14*b[2] - 18*b[3]
+	    + 16*c[0] + 16*c[1] + 16*c[2] + 16*c[3];
+
+	D = 0 - a[3]
+	    +  4*b[0] + 10*b[1] + 20*b[2] + 34*b[3]
+	    - 48*c[0] - 64*c[1] - 80*c[2] - 96*c[3]
+	    + 64*d[0] + 64*d[1] + 64*d[2] + 64*d[3];
+
+	ZIO_SET_CHECKSUM(zcp, A, B, C, D);
+}
+
+static void
+fletcher_4_avx2(const void *buf, uint64_t size, zio_cksum_t *unused)
+{
+	const uint64_t *ip = buf;
+	const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
+
+	for (; ip < ipend; ip += 2) {
+		asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
+		asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
+		asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
+		asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
+		asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
+	}
+}
+
+static void
+fletcher_4_avx2_byteswap(const void *buf, uint64_t size, zio_cksum_t *unused)
+{
+	static const struct {
+		uint64_t v[4] __attribute__((aligned(32)));
+	} mask = {
+		.v = { 0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B,
+		    0xFFFFFFFF00010203, 0xFFFFFFFF08090A0B }
+	};
+	const uint64_t *ip = buf;
+	const uint64_t *ipend = (uint64_t *)((uint8_t *)ip + size);
+
+	asm volatile("vmovdqa %0, %%ymm5"::"m"(mask));
+
+	for (; ip < ipend; ip += 2) {
+		asm volatile("vpmovzxdq %0, %%ymm4"::"m" (*ip));
+		asm volatile("vpshufb %ymm5, %ymm4, %ymm4");
+
+		asm volatile("vpaddq %ymm4, %ymm0, %ymm0");
+		asm volatile("vpaddq %ymm0, %ymm1, %ymm1");
+		asm volatile("vpaddq %ymm1, %ymm2, %ymm2");
+		asm volatile("vpaddq %ymm2, %ymm3, %ymm3");
+	}
+}
+
+static boolean_t fletcher_4_avx2_valid(void)
+{
+	return (zfs_avx_available() && zfs_avx2_available());
+}
+
+const fletcher_4_ops_t fletcher_4_avx2_ops = {
+	.init = fletcher_4_avx2_init,
+	.fini = fletcher_4_avx2_fini,
+	.compute = fletcher_4_avx2,
+	.compute_byteswap = fletcher_4_avx2_byteswap,
+	.valid = fletcher_4_avx2_valid,
+	.name = "avx2"
+};
+
+#endif /* defined(HAVE_AVX) && defined(HAVE_AVX2) */

module/zcommon/zfs_prop.c

@@ -35,6 +35,7 @@
 
 #include "zfs_prop.h"
 #include "zfs_deleg.h"
+#include "zfs_fletcher.h"
 
 #if defined(_KERNEL)
 #include <sys/systm.h>
@@ -695,12 +696,14 @@ zfs_prop_align_right(zfs_prop_t prop)
 static int __init
 zcommon_init(void)
 {
+	fletcher_4_init();
 	return (0);
 }
 
 static void __exit
 zcommon_fini(void)
 {
+	fletcher_4_fini();
 }
 
 module_init(zcommon_init);