153 lines
3.7 KiB
C
153 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mt8188-afe-common.h -- MediaTek 8188 audio driver definitions
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*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
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* Trevor Wu <trevor.wu@mediatek.com>
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* Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
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*/
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#ifndef _MT_8188_AFE_COMMON_H_
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#define _MT_8188_AFE_COMMON_H_
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#include <linux/list.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include "../common/mtk-base-afe.h"
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enum {
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MT8188_DAI_START,
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MT8188_AFE_MEMIF_START = MT8188_DAI_START,
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MT8188_AFE_MEMIF_DL2 = MT8188_AFE_MEMIF_START,
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MT8188_AFE_MEMIF_DL3,
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MT8188_AFE_MEMIF_DL6,
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MT8188_AFE_MEMIF_DL7,
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MT8188_AFE_MEMIF_DL8,
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MT8188_AFE_MEMIF_DL10,
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MT8188_AFE_MEMIF_DL11,
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MT8188_AFE_MEMIF_UL_START,
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MT8188_AFE_MEMIF_UL1 = MT8188_AFE_MEMIF_UL_START,
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MT8188_AFE_MEMIF_UL2,
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MT8188_AFE_MEMIF_UL3,
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MT8188_AFE_MEMIF_UL4,
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MT8188_AFE_MEMIF_UL5,
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MT8188_AFE_MEMIF_UL6,
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MT8188_AFE_MEMIF_UL8,
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MT8188_AFE_MEMIF_UL9,
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MT8188_AFE_MEMIF_UL10,
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MT8188_AFE_MEMIF_END,
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MT8188_AFE_MEMIF_NUM = (MT8188_AFE_MEMIF_END - MT8188_AFE_MEMIF_START),
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MT8188_AFE_IO_START = MT8188_AFE_MEMIF_END,
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MT8188_AFE_IO_DL_SRC = MT8188_AFE_IO_START,
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MT8188_AFE_IO_DMIC_IN,
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MT8188_AFE_IO_DPTX,
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MT8188_AFE_IO_ETDM_START,
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MT8188_AFE_IO_ETDM1_IN = MT8188_AFE_IO_ETDM_START,
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MT8188_AFE_IO_ETDM2_IN,
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MT8188_AFE_IO_ETDM1_OUT,
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MT8188_AFE_IO_ETDM2_OUT,
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MT8188_AFE_IO_ETDM3_OUT,
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MT8188_AFE_IO_ETDM_END,
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MT8188_AFE_IO_ETDM_NUM =
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(MT8188_AFE_IO_ETDM_END - MT8188_AFE_IO_ETDM_START),
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MT8188_AFE_IO_PCM = MT8188_AFE_IO_ETDM_END,
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MT8188_AFE_IO_UL_SRC,
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MT8188_AFE_IO_END,
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MT8188_AFE_IO_NUM = (MT8188_AFE_IO_END - MT8188_AFE_IO_START),
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MT8188_DAI_END = MT8188_AFE_IO_END,
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MT8188_DAI_NUM = (MT8188_DAI_END - MT8188_DAI_START),
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};
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enum {
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MT8188_TOP_CG_A1SYS_TIMING,
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MT8188_TOP_CG_A2SYS_TIMING,
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MT8188_TOP_CG_26M_TIMING,
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MT8188_TOP_CG_NUM,
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};
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enum {
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MT8188_AFE_IRQ_1,
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MT8188_AFE_IRQ_2,
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MT8188_AFE_IRQ_3,
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MT8188_AFE_IRQ_8,
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MT8188_AFE_IRQ_9,
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MT8188_AFE_IRQ_10,
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MT8188_AFE_IRQ_13,
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MT8188_AFE_IRQ_14,
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MT8188_AFE_IRQ_15,
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MT8188_AFE_IRQ_16,
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MT8188_AFE_IRQ_17,
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MT8188_AFE_IRQ_18,
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MT8188_AFE_IRQ_19,
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MT8188_AFE_IRQ_20,
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MT8188_AFE_IRQ_21,
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MT8188_AFE_IRQ_22,
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MT8188_AFE_IRQ_23,
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MT8188_AFE_IRQ_24,
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MT8188_AFE_IRQ_25,
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MT8188_AFE_IRQ_26,
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MT8188_AFE_IRQ_27,
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MT8188_AFE_IRQ_28,
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MT8188_AFE_IRQ_NUM,
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};
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enum {
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MT8188_ETDM_OUT1_1X_EN = 9,
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MT8188_ETDM_OUT2_1X_EN = 10,
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MT8188_ETDM_OUT3_1X_EN = 11,
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MT8188_ETDM_IN1_1X_EN = 12,
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MT8188_ETDM_IN2_1X_EN = 13,
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MT8188_ETDM_IN1_NX_EN = 25,
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MT8188_ETDM_IN2_NX_EN = 26,
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};
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enum {
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MT8188_MTKAIF_MISO_0,
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MT8188_MTKAIF_MISO_1,
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MT8188_MTKAIF_MISO_NUM,
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};
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struct mtk_dai_memif_irq_priv {
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unsigned int asys_timing_sel;
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};
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struct mtkaif_param {
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bool mtkaif_calibration_ok;
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int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM];
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int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM];
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int mtkaif_dmic_on;
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};
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struct clk;
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struct mt8188_afe_private {
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struct clk **clk;
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struct clk_lookup **lookup;
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struct regmap *topckgen;
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int pm_runtime_bypass_reg_ctl;
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spinlock_t afe_ctrl_lock; /* Lock for afe control */
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struct mtk_dai_memif_irq_priv irq_priv[MT8188_AFE_IRQ_NUM];
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struct mtkaif_param mtkaif_params;
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/* dai */
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void *dai_priv[MT8188_DAI_NUM];
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};
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int mt8188_afe_fs_timing(unsigned int rate);
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/* dai register */
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int mt8188_dai_adda_register(struct mtk_base_afe *afe);
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int mt8188_dai_etdm_register(struct mtk_base_afe *afe);
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int mt8188_dai_pcm_register(struct mtk_base_afe *afe);
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#define MT8188_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \
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{ \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = snd_soc_info_enum_double, \
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.get = xhandler_get, .put = xhandler_put, \
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.device = id, \
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.private_value = (unsigned long)&(xenum), \
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}
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#endif
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