396 lines
12 KiB
C
396 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE UCC Fast API Set - UCC Fast specific routines implementations.
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <asm/io.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/ucc.h>
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#include <soc/fsl/qe/ucc_fast.h>
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void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
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{
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printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
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printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
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printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
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printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
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printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
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printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
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printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
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printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
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printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
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&uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
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printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
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printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
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printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
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printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->urfset,
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ioread16be(&uccf->uf_regs->urfset));
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printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
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printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
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printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
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printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
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printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
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&uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
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printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
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&uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
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printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
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&uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
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}
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EXPORT_SYMBOL(ucc_fast_dump_regs);
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u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
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{
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switch (uccf_num) {
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case 0: return QE_CR_SUBBLOCK_UCCFAST1;
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case 1: return QE_CR_SUBBLOCK_UCCFAST2;
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case 2: return QE_CR_SUBBLOCK_UCCFAST3;
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case 3: return QE_CR_SUBBLOCK_UCCFAST4;
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case 4: return QE_CR_SUBBLOCK_UCCFAST5;
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case 5: return QE_CR_SUBBLOCK_UCCFAST6;
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case 6: return QE_CR_SUBBLOCK_UCCFAST7;
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case 7: return QE_CR_SUBBLOCK_UCCFAST8;
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default: return QE_CR_SUBBLOCK_INVALID;
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}
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}
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EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
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void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
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{
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iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
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}
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EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
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void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
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{
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struct ucc_fast __iomem *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Enable reception and/or transmission on this UCC. */
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gumr = ioread32be(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr |= UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 1;
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}
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if (mode & COMM_DIR_RX) {
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gumr |= UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 1;
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}
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iowrite32be(gumr, &uf_regs->gumr);
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}
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EXPORT_SYMBOL(ucc_fast_enable);
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void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
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{
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struct ucc_fast __iomem *uf_regs;
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u32 gumr;
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uf_regs = uccf->uf_regs;
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/* Disable reception and/or transmission on this UCC. */
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gumr = ioread32be(&uf_regs->gumr);
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if (mode & COMM_DIR_TX) {
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gumr &= ~UCC_FAST_GUMR_ENT;
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uccf->enabled_tx = 0;
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}
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if (mode & COMM_DIR_RX) {
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gumr &= ~UCC_FAST_GUMR_ENR;
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uccf->enabled_rx = 0;
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}
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iowrite32be(gumr, &uf_regs->gumr);
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}
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EXPORT_SYMBOL(ucc_fast_disable);
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int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
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{
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struct ucc_fast_private *uccf;
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struct ucc_fast __iomem *uf_regs;
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u32 gumr;
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int ret;
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if (!uf_info)
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return -EINVAL;
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/* check if the UCC port number is in range. */
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if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
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printk(KERN_ERR "%s: illegal UCC number\n", __func__);
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return -EINVAL;
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}
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/* Check that 'max_rx_buf_length' is properly aligned (4). */
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if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
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__func__);
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return -EINVAL;
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}
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/* Validate Virtual Fifo register values */
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if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
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printk(KERN_ERR "%s: urfs is too small\n", __func__);
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return -EINVAL;
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}
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if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
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return -EINVAL;
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}
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if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
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return -EINVAL;
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}
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if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
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return -EINVAL;
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}
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if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
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return -EINVAL;
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}
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if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
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return -EINVAL;
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}
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if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
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printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
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return -EINVAL;
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}
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uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
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if (!uccf) {
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printk(KERN_ERR "%s: Cannot allocate private data\n",
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__func__);
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return -ENOMEM;
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}
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uccf->ucc_fast_tx_virtual_fifo_base_offset = -1;
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uccf->ucc_fast_rx_virtual_fifo_base_offset = -1;
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/* Fill fast UCC structure */
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uccf->uf_info = uf_info;
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/* Set the PHY base address */
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uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
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if (uccf->uf_regs == NULL) {
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printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
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kfree(uccf);
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return -ENOMEM;
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}
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uccf->enabled_tx = 0;
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uccf->enabled_rx = 0;
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uccf->stopped_tx = 0;
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uccf->stopped_rx = 0;
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uf_regs = uccf->uf_regs;
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uccf->p_ucce = &uf_regs->ucce;
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uccf->p_uccm = &uf_regs->uccm;
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#ifdef CONFIG_UGETH_TX_ON_DEMAND
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uccf->p_utodr = &uf_regs->utodr;
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#endif
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#ifdef STATISTICS
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uccf->tx_frames = 0;
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uccf->rx_frames = 0;
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uccf->rx_discarded = 0;
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#endif /* STATISTICS */
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/* Set UCC to fast type */
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ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
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if (ret) {
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printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
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ucc_fast_free(uccf);
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return ret;
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}
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uccf->mrblr = uf_info->max_rx_buf_length;
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/* Set GUMR */
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/* For more details see the hardware spec. */
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gumr = uf_info->ttx_trx;
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if (uf_info->tci)
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gumr |= UCC_FAST_GUMR_TCI;
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if (uf_info->cdp)
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gumr |= UCC_FAST_GUMR_CDP;
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if (uf_info->ctsp)
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gumr |= UCC_FAST_GUMR_CTSP;
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if (uf_info->cds)
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gumr |= UCC_FAST_GUMR_CDS;
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if (uf_info->ctss)
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gumr |= UCC_FAST_GUMR_CTSS;
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if (uf_info->txsy)
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gumr |= UCC_FAST_GUMR_TXSY;
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if (uf_info->rsyn)
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gumr |= UCC_FAST_GUMR_RSYN;
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gumr |= uf_info->synl;
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if (uf_info->rtsm)
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gumr |= UCC_FAST_GUMR_RTSM;
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gumr |= uf_info->renc;
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if (uf_info->revd)
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gumr |= UCC_FAST_GUMR_REVD;
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gumr |= uf_info->tenc;
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gumr |= uf_info->tcrc;
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gumr |= uf_info->mode;
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iowrite32be(gumr, &uf_regs->gumr);
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/* Allocate memory for Tx Virtual Fifo */
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uccf->ucc_fast_tx_virtual_fifo_base_offset =
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qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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if (uccf->ucc_fast_tx_virtual_fifo_base_offset < 0) {
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printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
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__func__);
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ucc_fast_free(uccf);
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return -ENOMEM;
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}
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/* Allocate memory for Rx Virtual Fifo */
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uccf->ucc_fast_rx_virtual_fifo_base_offset =
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qe_muram_alloc(uf_info->urfs +
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UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
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UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
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if (uccf->ucc_fast_rx_virtual_fifo_base_offset < 0) {
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printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
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__func__);
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ucc_fast_free(uccf);
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return -ENOMEM;
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}
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/* Set Virtual Fifo registers */
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iowrite16be(uf_info->urfs, &uf_regs->urfs);
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iowrite16be(uf_info->urfet, &uf_regs->urfet);
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iowrite16be(uf_info->urfset, &uf_regs->urfset);
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iowrite16be(uf_info->utfs, &uf_regs->utfs);
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iowrite16be(uf_info->utfet, &uf_regs->utfet);
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iowrite16be(uf_info->utftt, &uf_regs->utftt);
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/* utfb, urfb are offsets from MURAM base */
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iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
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&uf_regs->utfb);
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iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
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&uf_regs->urfb);
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/* Mux clocking */
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/* Grant Support */
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ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
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/* Breakpoint Support */
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ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
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/* Set Tsa or NMSI mode. */
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ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
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/* If NMSI (not Tsa), set Tx and Rx clock. */
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if (!uf_info->tsa) {
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/* Rx clock routing */
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if ((uf_info->rx_clock != QE_CLK_NONE) &&
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ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
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COMM_DIR_RX)) {
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printk(KERN_ERR "%s: illegal value for RX clock\n",
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__func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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/* Tx clock routing */
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if ((uf_info->tx_clock != QE_CLK_NONE) &&
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ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
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COMM_DIR_TX)) {
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printk(KERN_ERR "%s: illegal value for TX clock\n",
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__func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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} else {
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/* tdm Rx clock routing */
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if ((uf_info->rx_clock != QE_CLK_NONE) &&
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ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->rx_clock,
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COMM_DIR_RX)) {
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pr_err("%s: illegal value for RX clock", __func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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/* tdm Tx clock routing */
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if ((uf_info->tx_clock != QE_CLK_NONE) &&
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ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->tx_clock,
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COMM_DIR_TX)) {
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pr_err("%s: illegal value for TX clock", __func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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/* tdm Rx sync clock routing */
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if ((uf_info->rx_sync != QE_CLK_NONE) &&
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ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->rx_sync,
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COMM_DIR_RX)) {
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pr_err("%s: illegal value for RX clock", __func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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/* tdm Tx sync clock routing */
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if ((uf_info->tx_sync != QE_CLK_NONE) &&
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ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->tx_sync,
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COMM_DIR_TX)) {
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pr_err("%s: illegal value for TX clock", __func__);
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ucc_fast_free(uccf);
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return -EINVAL;
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}
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}
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/* Set interrupt mask register at UCC level. */
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iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
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/* First, clear anything pending at UCC level,
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* otherwise, old garbage may come through
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* as soon as the dam is opened. */
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/* Writing '1' clears */
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iowrite32be(0xffffffff, &uf_regs->ucce);
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*uccf_ret = uccf;
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return 0;
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}
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EXPORT_SYMBOL(ucc_fast_init);
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void ucc_fast_free(struct ucc_fast_private * uccf)
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{
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if (!uccf)
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return;
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qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
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qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
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if (uccf->uf_regs)
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iounmap(uccf->uf_regs);
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kfree(uccf);
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}
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EXPORT_SYMBOL(ucc_fast_free);
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